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7.7.9 External Power Control Pending Register (EPCPR)
PSC Registers
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The external power control pending register (EPCPR) is shown in
and described in
.
Figure 7-11. External Power Control Pending Register (EPCPR)
31
1
0
Reserved
EPC[1]
R-0
R-0
LEGEND: R = Read, n = value at reset
Table 7-14. External Power Control Pending Register (EPCPR) Field Descriptions
Bit
Field
Value
Description
31-1
Reserved
0
Reserved
0
EPC[1]
External power control pending bit.
The PSC sets this bit, indicating it is ready for an external controller to apply
power to the external power pins of the power domain.
0
The PSC is not requesting external power control.
1
The PSC requests external power control.
Power and Sleep Controller
80
SPRUFX7 – July 2008