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9.10.13 VDAC_CONFIG - Video Dac Configuration
System Control Register Descriptions
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the VDAC_CONFIG register provides control of the Video DAC.
Figure 9-12. VDAC_CONFIG - Video Dac Configuration
31
30
29
26
25
24
Reserved
TRESB4R4
TRESB4R2
R-0
R-0
R/W-0xC
R/W-0x8
23
22
21
18
17
16
TRESB4R2
TRESB4R1
TRIMBITS
R/W-0x8
R/W-0xC
R/W-0x37
15
11
10
9
8
TRIMBITS
PWD_BGZ
SPEED
TVINT
R/W-0x37
R/W-0
R/W-1
R-x
7
6
4
3
2
1
0
PWD_VBFUZ
VREFSET
ACCUP_EN
DINV
Reserved
Reserved
R/W-0
R/W-3
R/W-1
R/W-1
R-1
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 9-15. VDAC_CONFIG - Video Dac Configuration Field Descriptions
Bit
Field
Value
Description
31-30
Reserved
0
Reserved
29-26
TRESB4R4
0-Fh
Resistance trimming control bit for VREF
25-22
TRESB4R2
0-Fh
Resistance trimming control bit for VREF
21-18
TRESB4R1
0-Fh
Resistance trimming control bit for VREF
17-11
TRIMBITS
0-7Fh
PNP transistor trimming control bit for VREF
10
PWD_BGZ
Power Down of VREFF
0
Power down
1
Power up
9
SPEED
Faster operation of VREF transfer
0
Normal
1
Faster
8
TVINT
TV cable connect status from DAC
0
Cable connected
1
Cable disconnected
7
PWD_VBFUZ
Power down of video buffer
0
Power down
1
Power up
6-4
VREFSET
0-7h
VREF setting to video buffer
3
ACCUP_EN
AC capacitor coupling externally to video buffer
0
Disable the coupling
1
Enable the coupling
2
DINV
Data invert from VENC (inside the DAC)
0
No inversion - use only when VDAC is used without VREF and buffer
1
Inversion - When VDAC is used with VFEF and buffer
1
Reserved
1
Reserved
0
Reserved
0
Reserved
System Control Module
134
SPRUFX7 – July 2008