![background image](http://html.mh-extra.com/html/texas-instruments/tms320dm335/tms320dm335_user-manual_1097123043.webp)
6.5.2.1.1 GO Operation
GO operation:
GOSET set,
GOSTAT
changed to 1
PLLDIV.RATIO
modified, but
SYSCLKn not
changed yet
End of GO operation. GOSTAT automatically
clears to 0 to indicate completion of clock rate change
PLLSTAT
GOSTAT
SYSCLKw
/1 to /2,
set ALN1=1
SYSCLKx
/2 to /4,
set ALN2=1
SYSCLKy
/3 to /3,
set ALN3=1
SYSCLKz
/4 to /4,
set ALN4=0
SYSCLKs rising edge aligned
6.5.2.1.2 Software Steps to Modify PLLDIVn Ratios
www.ti.com
PLL Configuration
Writes to the RATIO field in the PLLDIVn registers do not change the dividers’ actual divide ratios
immediately. The PLLDIVn dividers only change to the new RATIO rates during a GO operation. This
section discusses the GO operation and how the SYSCLKs are aligned. The PLL controller clock align
control register (ALNCTL) determines which SYSCLKs must be aligned. Before a GO operation, you must
program ALNCTL so that the appropriate clocks are aligned during the GO operation. Always program
ALNCTL so that all SYSCLKs are aligned. A GO operation is initiated by setting the GOSET bit in
PLLCMD to 1. During a GO operation:
•
Any SYSCLKn with the corresponding ALNn bit in ALNCTL set to 1 is paused at the low edge. Then
the PLL controller restarts all these SYSCLKs simultaneously, aligned at the rising edge. When the
SYSCLKs are restarted, SYSCLKn toggles at the rate programmed in the RATIO field in PLLDIVn.
•
Any SYSCLKn with the corresponding ALNn bit in ALNCTL cleared to 0 remains free-running during a
GO operation. SYSCLKn is not modified to the new RATIO rate in PLLDIVn. SYSCLKn is not aligned
to other SYSCLKs. Do not program any ALNn bit in ALNCTL to 0; always program ALNCTL so that all
SYSCLKs are aligned.
•
The GOSTAT bit in PLLSTAT is set to 1 throughout the duration of a GO operation.
is an example showing how the clocks are rising-edge aligned during a GO operation. Notice
that even though the SYSCLKy ratio remains the same, it is still stopped since ALN3 = 1 in ALNCTL.
Figure 6-3. Clock Ratio Change and Alignment with Go Operation
To modify the PLLDIVn ratios, perform the following steps:
1. Check that the GOSTAT bit in PLLSTAT is cleared to 0 to show that no GO operation is currently in
progress.
2. Program the RATIO field in PLLDIVn to the desired new divide-down rate. If the RATIO field changed,
the PLL controller will flag the change in the corresponding bit of DCHANGE.
3. Set the respective ALNn bits in ALNCTL to 1 to align any SYSCLKs after the GO operation.
4. Set the GOSET bit in PLLCMD to 1 to initiate the GO operation to change the divide values and align
the SYSCLKs as programmed.
5. Read the GOSTAT bit in PLLSTAT to make sure the bit goes back to 0 to indicate that the GO
operation has completed.
SPRUFX7 – July 2008
PLL Controllers (PLLCs)
43