![background image](http://html.mh-extra.com/html/texas-instruments/tms320dm335/tms320dm335_user-manual_1097123138.webp)
9.10.16 MISC - Miscellaneous Control
9.10.17 MSTPRI0 - Master Priorities 0
System Control Register Descriptions
www.ti.com
The MISC register include miscellaneous control functions.
Figure 9-15. MISC - Miscellaneous Control
31
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
TIMER2_WDT
DEV_SPEED
PLL1_POSTDIV
AIM_WAIST
R-0
R/W-1
R-eFuse
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 9-18. MISC - Miscellaneous Control Field Descriptions
Bit
Field
Value
Description
31-5
RESERVED
0
Reserved.
4
TIMER2_WDT
TIMER2 Definition (Normal vs. WDT).
0
TIMER2 is normal Timer.
1
TIMER2 is WDT.
3-2
DEV_SPEED
0-3h
Device speed grade eFuse status. these bits indicate the device speed grades.
1
PLL1_POSTDIV
PLL1 post-divider selection.
0
Sets PLL1 post-divider equal to 1. Setting this bit to 0 has no effect when DEV_SPEED equals 1 or
3.
1
Sets PLL1 post-divider equal to 2.
0
AIM_WAIST
ARM Internal Memory Wait States.
0
1 wait state to IRAM.
1
0 wait state to IRAM. Set this bit for zero wait-state only if the ARM clock frequency is less than or
equal to 150 MHz.
The MSTPRI0 registers provides control of the bus masters' DMA priorities.
Figure 9-16. MSTPRI0 - Master Priorities 0
31
7
6
4
3
2
0
Reserved
ARM_CFGP
Reserved
ARM_DMAP
R-0
R/W-0x1
R-0
R/W-0x1
LEGEND: R/W = Read/Write, R = Read only; n = value at reset
Table 9-19. MSTPRI0 - Master Priorities 0 Field Descriptions
Bit
Field
Value
Description
31-7
Reserved
0
Reserved
6-4
ARM_CFGP
0-7h
ARM CFG bus priority
3
Reserved
0
Reserved
2-0
ARM_DMAP
0-7h
ARM DMA priority
System Control Module
138
SPRUFX7 – July 2008