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10.4.2 PLL Configuration
10.4.3 Module Configuration
10.4.4 ARM Boot Mode Configuration
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Default Device Configurations
Note:
The device configuration pins are multiplexed with AEMIF pins. After the device configuration
pins are sampled at reset, they automatically change to function as AEMIF pins. Pin
multiplexing is described in
.
Table 10-3. Device Configuration
Default Setting
Device
(by internal
Configuration
Sampled
pull-up/
Input
Function
Pin
pull-down)
Device Configuration Affected
BTSEL[1:0]
Selects ARM boot mode
EM_A[13:12]
00
If any ROM boot mode is selected,
00 = Boot from ROM
(NAND)
GIO61 is used to indicated boot status.
(NAND)
If NAND boot is selected, CE0 is used
01 = Boot from AEMIF
for NAND. Use AECFG[3:0] to configure
10 = Boot from ROM
AEMIF pins for NAND.
(MMC/SD)
If AEMIF boot is selected, CE0 is used
11 = Boot from ROM
for AEMIF device (OneNAND, ROM).
(UART)
Use AECFG[3:0] to configure AEMIF
pins for NAND.
If MMC/SD boot is selected, MMC/SD0
is used.
AECFG[3:0]
Selects the AEMIF pin
EM_A[11:8]
1101
AEMIF pin configuration. Refer to
configuration.
(NAND)
pin-muxing information in
.
Note that AECFG[3:0] affects pin
configuration for both AEMIF
(BTSEL[1:0]=01) and NAND
(BTSEL[1:0]=00) boot modes.
After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The
PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1
(typically 24 MHz) drives the chip after reset. For more information, see
and
. The
default state of the PLLs is reflected by the default state of the register bits in the PLLC registers.
Only a subset of modules are enabled after reset by default.
in
shows which modules
are enabled after reset. Furthermore, as shown in
, the following modules are enabled
depending on the sampled state of the device configuration pins: EMDA (CC and TC0), AEMIF,
MMC/SD0, UART0, and Timer0. For example, UART0 is enabled after reset when the device
configuration pins (BTSEL[1:0] = 11 - Enable UART) select UART boot mode.
The input pins BTSEL[1:0] determine whether the ARM will boot from its ROM or from the Asynchronous
EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] = 00, 10, or 11), a jump to the start of internal
ROM (address 0x0000: 8000) is forced into the first fetched instruction word. The embedded ROM boot
loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine
the desired boot method, and branches to the appropriate boot routine (i.e., a NAND, MMC/SD, or UART
loader routine) .
If AEMIF boot is selected (BTSEL[1:0] = 01), a jump to the start of AEMIF (address 0x0200: 0000) is
forced into the first fetched instruction word. The ARM then continues executing from external
asynchronous memory using the default AEMIF timings until modified by software.
Note:
For AEMIF boot, OneNAND must be connected to the first AEMIF chip select space
(EM_CE0). The AEMIF does not support direct execution from NAND Flash.
SPRUFX7 – July 2008
Reset
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