7.1
Introduction
arm_clock
arm_mreset
arm_power
AINTC
ARM
module_power
module_mreset
MODx
module_clock
Always on
domain
Interrupt
PSC
clks
PLLC
Emulation
RESETN
VDD
DMSoC
7.2
Power Domain and Module Topology
SPRUFX7 – July 2008
Power and Sleep Controller
In the DM335 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of
system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in
. Many of
the operations of the PSC are transparent to software, such as power-on-reset operations. However, the
PSC provides you with an interface to control several important clock and reset operations. The clock and
reset operations are the focus of this chapter.
The PSC includes the following features:
•
Manages chip power-on/off, clock on/off, and resets
•
Provides a software interface to:
–
Control module clock ON/OFF
–
Control module resets
•
Supports IcePick emulation features: power, clock, and reset
Figure 7-1. Power and Sleep Controller (PSC)
The DM335 system includes one power domain and forty-one separate modules, as shown in
and summarized in
. The device's power domain is always on when the chip is on, and it is
referred to as the AlwaysOn power domain. The AlwaysOn domain is powered by the V
DD
pins of the
device chip (see the device-specific Data Manual). All of the device modules lie within the AlwaysOn
power domain.
shows the default state of each module after reset (power-on-reset, warm reset, and max reset).
These states are defined in the following sections. The default state of some modules is determined by the
boot select pins BTSEL[1:0]. For example, if UART boot mode is selected (BTSEL[1:0]=11), then the
default state for the UART module is Enable. See
and
for additional information on
reset, default configurations, and booting.
SPRUFX7 – July 2008
Power and Sleep Controller
63