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4.2
Memory Interfaces Overview
4.2.1 DDR2 EMIF
4.2.2 External Memory Interface
4.2.2.1
Asynchronous EMIF (AEMIF)
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Memory Interfaces Overview
This section describes the different memory interfaces.
The device supports several memory and external device interfaces, including the following:
•
DDR2 / mDDR Synchronous DRAM
•
Asynchronous EMIF
•
NAND Flash
•
OneNAND flash
The DDR2 EMIF interface, sometimes referred to as EMIF3.0 in the device documentation, is a dedicated
interface to DDR and MDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM
devices and supports only 16-bit interfaces.
DDR SDRAM plays a key role in a DM335-based system. Such a system is expected to require a
significant amount of high-speed external memory for the following:
•
Buffering input image data from sensors or video sources,
•
Intermediate buffering for processing/resizing of image data in the VPFE,
•
Numerous OSD display buffers
•
Intermediate buffering for large raw Bayer data image files while performing still camera processing
functions
•
Buffering for intermediate data while performing video encode and decode functions
•
Storage of executable firmware for the ARM
The external memory interface (EMIF) provides an 8-bit or 16-bit data bus, an address bus width of up to
14-bits, and 2 dedicated chip selects, along with memory control signals. The EMIF module supports:
•
Asynchronous memories (SRAM, Linear flash, etc.)
•
NAND flash memories
•
OneNAND flash memories
The asynchronous EMIF (AEMIF) mode supports the following features:
•
SRAM on up to two asynchronous chip selects
•
Supports 8-bit or 16-bit data bus widths
•
Programmable asynchronous cycle timings
•
Supports extended waits
•
Supports Select Strobe mode
•
Supports booting the device ARM processor from CE0 (e.g., SRAM) via direct execution
SPRUFX7 – July 2008
Memory Mapping
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