![background image](http://html.mh-extra.com/html/texas-instruments/tms320dm335/tms320dm335_user-manual_1097123003.webp)
Contents
1
Introduction
1.1
Device Overview
1.2
Block Diagram
1.3
ARM Subsystem in DM335
...................................................................................................
2
ARM Subsystem Overview
.........................................................................................
2.1
Purpose of the ARM Subsystem
...........................................................................................
2.2
Components of the ARM Subsystem
....................................................................................
2.3
References
3
ARM Core
3.1
3.2
Operating States/Modes
3.3
Processor Status Registers
.................................................................................................
3.4
Exceptions and Exception Vectors
.......................................................................................
3.5
The 16-BIS/32-BIS Concept
..................................................................................................
3.5.1
16-BIS/32-BIS Advantages
.............................................................................................
3.6
Coprocessor 15 (CP15)
3.6.1
Addresses in an ARM926EJ-S System
...............................................................................
3.6.2
Memory Management Unit
.............................................................................................
3.6.3
Caches and Write Buffer
...............................................................................................
3.7
Tightly Coupled Memory
3.8
Embedded Trace Support
....................................................................................................
4
Memory Mapping
4.1
Memory Map
4.1.1
ARM Internal Memories
.................................................................................................
4.1.2
External Memories
4.1.3
Peripherals
4.2
Memory Interfaces Overview
................................................................................................
4.2.1
DDR2 EMIF
4.2.2
External Memory Interface
.............................................................................................
5
Device Clocking
5.1
Overview
5.2
Peripheral Clocking Considerations
.....................................................................................
5.2.1
Video Processing Back End Clocking
................................................................................
5.2.2
USB Clocking
6
PLL Controllers (PLLCs)
............................................................................................
6.1
PLL Controller Module
6.2
PLLC1
SPRUFX7 – July 2008
Table of Contents
3