3.6.2 Memory Management Unit
3.6.3 Caches and Write Buffer
Coprocessor 15 (CP15)
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The ARM926EJ-S MMU provides virtual memory features required by operating systems such as
SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls
the address translation, permission checks, and memory region attributes for both data and instruction
accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information
held in the page tables.
The MMU features are as follows:
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access protection scheme.
•
Mapping sizes are 1 MB (sections), 64 KB (large pages), 4 KB (small pages) and 1 KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
Hardware page table walks
•
Invalidate entire TLB, using CP15 register 8
•
Invalidate TLB entry, selected by MVA, using CP15 register 8
•
Lockdown of TLB entries, using CP15 register 10
Note:
See
of the Memory Management Unit of the ARM926EJ-S TRM, downloadable
from
for more detailed information.
The ARM926EJ-S processor includes:
•
An instruction cache (Icache)
•
A data cache (Dcache)
•
A write buffer
The size of the data cache is 8KB, instruction cache is 16KB, and write buffer is 17 bytes.
The caches have the following features:
•
Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)
•
Four-way set associative, with a cache line length of eight words per line (32 bytes per line), and two
dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
Perform critical-word first cache refilling
•
Cache lockdown registers enable control over which cache ways are used for allocation on a linefill,
providing a mechanism for both lockdown and controlling cache pollution.
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the
TAGRAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations to provide efficient invalidation of the following:
–
The entire Dcache or Icache
–
Regions of the Dcache or Icache
–
The entire Dcache
–
Regions of virtual memory
•
They also provide operations for efficient cleaning and invalidation of the following:
–
The entire Dcache
–
Regions of the Dcache
–
Regions of virtual memory
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ARM Core
SPRUFX7 – July 2008