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3.4
Exceptions and Exception Vectors
3.5
The 16-BIS/32-BIS Concept
3.5.1 16-BIS/32-BIS Advantages
Exceptions and Exception Vectors
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Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that
occur in an ARM system are given below:
•
Reset exception: processor reset
•
FIQ interrupt: fast interrupt
•
IRQ interrupt: normal interrupt
•
Abort exception: abort indicates that the current memory access could not be completed. The abort
could be a pre-fetch abort or a data abort.
•
SWI interrupt: use software interrupt to enter supervisor mode.
•
Undefined exception: occurs when the processor executes an undefined instruction
The exceptions in the order of highest priority to lowest priority are: reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction, and SWI. SWI and undefined instruction have the same priority. Depending
upon the status of VINTH signal or the register setting in CP15, the vector table can be located at address
0x00000000 (VINTH = 0) or at address 0xFFFF0000 (VINTH = 1). .
Note:
This is a feature of the ARM926EJ-S core. However, in this DMSoC there is no memory in
the address region starting at 0xFFFF0000, so do not set VINTH.
The default vector table is shown in
Note:
See ARM926EJ-S TRM, downloadable from
for more detailed
information.
Table 3-1. Exception Vector Table for ARM
Vector Offset Address
Exception
Mode on entry
I Bit State on Entry
F Bit State on Entry
0h
Reset
Supervisor
Set
Set
04h
Undefined instruction
Undefined
Set
Unchanged
08h
Software interrupt
Supervisor
Set
Unchanged
0Ch
Pre-fetch abort
Abort
Set
Unchanged
10h
Data abort
Abort
Set
Unchanged
14h
Reserved
-
-
-
18h
IRQ
IRQ
Set
Unchanged
1Ch
FIQ
FIQ
Set
Set
The key idea behind 16-BIS is that of a super-reduced instruction set. Essentially, the ARM926EJ-S
processor has two instruction sets:
•
ARM mode or 32-BIS: the standard 32-bit instruction set
•
Thumb mode or 16-BIS: a 16-bit instruction set
The 16-bit instruction length (16-BIS) allows the 16-BIS to approach twice the density of standard 32-BIS
code while retaining most of the 32-BIS’s performance advantage over a traditional 16-bit processor using
16-bit registers. This is possible because 16-BIS code operates on the same 32-bit register set as 32-BIS
code. 16-bit code can provide up to 65% of the code size of the 32-bit code and 160% of the performance
of an equivalent 32-BIS processor connected to a 16-bit memory system.
16-bit instructions operate with the standard 32-bit register configuration, allowing excellent
inter-operability between 32-BIS and 16-BIS states. Each 16-bit instruction has a corresponding 32-bit
instruction with the same effect on the processor model. The major advantage of a 32-bit architecture over
22
ARM Core
SPRUFX7 – July 2008