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8.4.1 Fast Interrupt Request Status Register 0 (FIQ0)
INTC Registers
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The fast interrupt request status register 0 (FIQ0) is shown in
and described in
Figure 8-5. Interrupt Status of INT[31:0] (if mapped to FIQ)
31
0
FIQ[31:0]
R/W-1
LEGEND: R/W = Read/Write; n = value at reset
Table 8-3. Interrupt Status of INT[31:0] (if mapped to FIQ) Field Descriptions
Bit
Field
Value
Description
31-0
FIQ[31:0]
Interrupt status of INTx, if mapped to FIQ.
0
Rd: Interrupt occurred
1
Wr: Acknowledge interrupt
Interrupt Controller
94
SPRUFX7 – July 2008