7.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1)
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PSC Registers
The module error clear 1 (mod 32-41) register (MERRCR1) is shown in
and described in
.
Figure 7-8. Module Error Clear Register 1 (mod 32-41) (MERRCR1)
31
16
Reserved
R-0
R-0
15
9
8
0
Reserved
M[9]
R-0
R-0
LEGEND: R/W = Read/Write, R = Read; n = value at reset
Table 7-11. Module Error Clear Register 1 (mod 32-41) (MERRCR1) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved
8-0
M[9]
Clears the interrupt bit set in the corresponding MERRPR1 register bit field
and the MDSTAT interrupt bit fields. This pertains to modules 32-41.
0
A write of 0 has no effect.
1
Clears module interrupt.
SPRUFX7 – July 2008
Power and Sleep Controller
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