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8.4.16 Interrupt Priority Register 5 (INTPRI5)

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INTC Registers

The interrupt priority register 5 (INTPRI5) is shown in

Figure 8-20

and described in

Table 8-18

Figure 8-20. Interrupt Priority Register 5 (INTPRI5)

Reserved

INT47

Reserved

INT46

Reserved

INT45

Reserved

INT44

R-0

R/W-7

R-0

R/W-7

R-0

R/W-7

R-0

R/W-7

Reserved

INT43

Reserved

INT42

Reserved

INT41

Reserved

INT40

R-0

R/W-7

R-0

R/W-7

R-0

R/W-7

R-0

R/W-7

LEGEND: R/W = Read/Write, R = Read; n = value at reset

Table 8-18. Interrupt Priority Register 5 (INTPRI5) Field Descriptions

Bit

Field

Value

Description

Reserved

30-28

INT47

0-7h

Selects INT47 priority level.

Reserved

26-24

INT46

0-7h

Selects INT46 priority level.

Reserved

22-20

INT45

0-7h

Selects INT45 priority level.

Reserved

18-16

INT44

0-7h

Selects INT44 priority level.

Reserved

14-12

INT43

0-7h

Selects INT43 priority level.

Reserved

10-8

INT42

0-7h

Selects INT42 priority level.

Reserved

6-4

INT41

0-7h

Selects INT41 priority level.

Reserved

2-0

INT40

0-7h

Selects INT40 priority level.

SPRUFX7 – July 2008

Interrupt Controller

109

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Summary of Contents for TMS320DM335

Page 1: ...TMS320DM335 Digital Media System on Chip DMSoC ARM Subsystem User s Guide Literature Number SPRUFX7 July 2008 ...

Page 2: ...2 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 3: ...15 23 3 6 1 Addresses in an ARM926EJ S System 23 3 6 2 Memory Management Unit 24 3 6 3 Caches and Write Buffer 24 3 7 Tightly Coupled Memory 26 3 8 Embedded Trace Support 27 4 Memory Mapping 29 4 1 Memory Map 29 4 1 1 ARM Internal Memories 30 4 1 2 External Memories 30 4 1 3 Peripherals 30 4 2 Memory Interfaces Overview 33 4 2 1 DDR2 EMIF 33 4 2 2 External Memory Interface 33 5 Device Clocking 35 ...

Page 4: ...n Control Register ALNCTL 57 6 6 14 PLLDIV Ratio Change Status Register DCHANGE 58 6 6 15 Clock Enable Control Register CKEN 59 6 6 16 Clock Status Register CKSTAT 60 6 6 17 SYSCLK Status Register SYSTAT 61 6 6 18 PLL Controller Divider 4 Register PLLDIV4 62 7 Power and Sleep Controller 63 7 1 Introduction 63 7 2 Power Domain and Module Topology 63 7 3 Power Domain and Module States Defined 66 7 3...

Page 5: ...egister 1 FIQ1 95 8 4 3 Interrupt Request Status Register 0 IRQ0 96 8 4 4 Interrupt Request Status Register 1 IRQ1 97 8 4 5 Fast Interrupt Request Entry Address Register FIQENTRY 98 8 4 6 Interrupt Request Entry Address Register IRQENTRY 99 8 4 7 Interrupt Enable Register 0 EINT0 100 8 4 8 Interrupt Enable Register 1 EINT1 101 8 4 9 Interrupt Operation Control Register INTCTL 102 8 4 10 EABASE 103...

Page 6: ...10 10 DDR_SLEW DDR Slew 131 9 10 11 CLKOUT CLKOUT Divisor Output Control 132 9 10 12 DEVICE_ID Device ID 133 9 10 13 VDAC_CONFIG Video Dac Configuration 134 9 10 14 TIMER64_CTL Timer64 Input Control 135 9 10 15 USB_PHY_CTRL USB PHY Control 136 9 10 16 MISC Miscellaneous Control 138 9 10 17 MSTPRI0 Master Priorities 0 138 9 10 18 Master Priorities 1 MSTPRI1 Register 139 9 10 19 VPSS_CLK_CTRL VPSS C...

Page 7: ... PLLC Overview 168 12 3 Clock Management 169 12 3 1 Module Clock Disable 169 12 3 2 Module Clock Frequency Scaling 169 12 3 3 PLL Bypass and Power Down 169 12 4 ARM Sleep Mode Management 169 12 4 1 ARM Wait For Interrupt Sleep Mode 169 12 5 System Sleep Modes 170 12 5 1 Deep Sleep Mode 170 12 6 I O Management 170 12 6 1 USB Phy Power Down 170 12 6 2 Video DAC Power Down 171 12 6 3 DDR Self Refresh...

Page 8: ...D 72 7 4 Interrupt Evaluation Register INTEVAL 73 7 5 Module Error Pending Register 0 mod 0 31 MERRPR0 74 7 6 Module Error Pending Register 1 mod 32 41 MERRPR1 75 7 7 Module Error Clear Register 0 mod 0 31 MERRCR0 76 7 8 Module Error Clear Register 1 mod 32 41 MERRCR1 77 7 9 Power Error Pending Register PERRPR 78 7 10 Power Error Clear Register PERRCR 79 7 11 External Power Control Pending Registe...

Page 9: ...KOUT div out Control 132 9 11 DEVICE_ID Device ID 133 9 12 VDAC_CONFIG Video Dac Configuration 134 9 13 TIMER64_CTL Timer64 Input Control 135 9 14 USB_PHY_CTRL USB PHY Control 136 9 15 MISC Miscellaneous Control 138 9 16 MSTPRI0 Master Priorities 0 138 9 17 Master Priorities 1 MSTPRI1 Register 139 9 18 VPSS_CLK_CTRL VPSS Clock Mux Control 140 9 19 Deep Sleep Mode Configuration DEEPSLEEP Register 1...

Page 10: ...egister CKSTAT Field Descriptions 60 6 20 SYSCLK Status Register SYSTAT Field Descriptions 61 6 21 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions 62 7 1 Module Configuration 65 7 2 Module States 66 7 3 IcePick Emulation Commands 67 7 4 PSC Interrupt Events 68 7 5 PSC Registers 71 7 6 Peripheral Revision and Class Information Register PID Field Descriptions 72 7 7 Interrupt Evaluation...

Page 11: ...9 4 PINMUX0 Pin Mux 0 Video In Pin Mux Register Field Descriptions 118 9 5 PINMUX1 Pin Mux 1 Video Out Pin Mux Register Field Descriptions 120 9 6 PINMUX2 Pin Mux 2 AEMIF Pin Mux Register Field Descriptions 122 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions 124 9 8 PINMUX4 Pin Mux 4 Misc Pin Mux Register Field Descriptions 127 9 9 BOOTCFG Boot Configuration Field Descriptions 1...

Page 12: ... Signatures and Special Modes 161 11 6 UART Data Sequences 166 11 7 Host Utility Data Format 167 11 8 CRC32 Table Transfer 167 12 1 Power Management Features 168 List of Tables 12 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 13: ... S ARM9 master control of the device In general the ARM is responsible for configuration and control of the device including the components of the ARM Subsystem the peripherals and the external memories SPRUFX8 TMS320DM335 Digital Media System on Chip DMSoC Video Processing Front End VPFE Reference Guide This document describes the Video Processing Front End VPFE in the TMS320DM335 Digital Media S...

Page 14: ... controller in the TMS320DM335 Digital Media System on Chip DMSoC The MMC SD card is used in a number of applications to provide removable data storage The MMC SD controller provides an interface to external MMC and SD cards The communication between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUFY6 TMS320DM335 Digital Media System on Chip DMSoC Pulse Width Modula...

Page 15: ... controller in the TMS320DM335 Digital Media System on Chip DMSoC The DDR2 mDDR memory controller is used to interface with JESD79D 2A standard compliant DDR2 SDRAM and mobile DDR devices SPRUFZ3 TMS320DM335 Digital Media System on Chip DMSoC Audio Serial Port ASP Reference Guide This document describes the operation of the audio serial port ASP audio interface in the TMS320DM335 Digital Media Sys...

Page 16: ...luation Board DVEVM allowing customers to utilize their same code for their new DM335 processor focused designs The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display Through its user interface technology such as a four level on screen display developers are able to create picture within picture and video within video as well as innovati...

Page 17: ...ocessor in the ARMSS acts as the overall system controller The ARM CPU performs general system control tasks such as system initialization configuration power management user interface and user command implementation Chapter 2 describes the ARMSS components and system control functions that the ARM core performs SPRUFX7 July 2008 Introduction 17 Submit Documentation Feedback ...

Page 18: ...vice consists of the following components ARM926EJ S RISC processor including Coprocessor 15 CP15 MMU 16KB Instruction cache 8KB Data cache Write Buffer Java accelerator ARM Internal Memories 32KB Internal RAM 32 bit wide access 8KB Internal ROM ARM bootloader for non AEMIF boot options Embedded Trace Module and Embedded Trace Buffer ETM ETB System Control Peripherals ARM Interrupt Controller PLL ...

Page 19: ...ule CFALD Video Processing Back End VPBE On Screen Display OSD Video Encoder Engine VENC Figure 2 1 shows the functional block diagram of the ARM Subsystem Figure 2 1 ARM Subsystem Block Diagram See the following related documents for more information DM335 Data Manual SPRS528 Provides a high level overview of the DM335 system DM335 Peripheral Reference Guides For various peripherals on the device...

Page 20: ...trade off between high performance and high code density This includes features for efficient execution of Java byte codes and providing Java performance similar to Just in Time JIT Java interpreter without associated code overhead The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging The ARM926EJ S processor has a Harvard...

Page 21: ... different modes The stack pointer SP automatically changes to the SP of the mode that was entered Note See the ARM926EJ S TRM downloadable from http www arm com for more detailed information The processor status register PSR controls the enabling and disabling of interrupts and setting the mode of operation of the processor PSR 7 0 are the processor control bits PSR 27 8 are reserved bits and PSR...

Page 22: ...tailed information Table 3 1 Exception Vector Table for ARM Vector Offset Address Exception Mode on entry I Bit State on Entry F Bit State on Entry 0h Reset Supervisor Set Set 04h Undefined instruction Undefined Set Unchanged 08h Software interrupt Supervisor Set Unchanged 0Ch Pre fetch abort Abort Set Unchanged 10h Data abort Abort Set Unchanged 14h Reserved 18h IRQ IRQ Set Unchanged 1Ch FIQ FIQ ...

Page 23: ...ching from 16 bit code to 32 bit code is folded into sub routine entry time Various portions of a system can be optimized for speed or for code density by switching between 16 BIS and 32 BIS execution as appropriate Note See the ARM926EJ S TRM downloadable from http www arm com for more detailed information The system control coprocessor CP15 is used to configure and control instruction and data c...

Page 24: ...buffer The size of the data cache is 8KB instruction cache is 16KB and write buffer is 17 bytes The caches have the following features Virtual index virtual tag addressed using the Modified Virtual Address MVA Four way set associative with a cache line length of eight words per line 32 bytes per line and two dirty bits in the Dcache Dcache supports write through and write back or copy back cache o...

Page 25: ... and a four address buffer The Dcache write back has eight data word entries and a single address entry The MCR drain write buffer enables both write buffers to be drained under software control The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ S processor to be put into a low power state until an interrupt occurs Note See Chapter 4 of the Caches and Write Buffer ...

Page 26: ...ster 0 The instruction for reading the TCM status is given below MRC p15 0 Rd c0 c0 2 read TCM status register where Rd is any register where the status data is read into the register The format of the data in the TCM register is as shown below 31 17 16 SBZ U DTCM NP 15 1 0 SBZ U ITCM NP If the DTCM bit is 0 Data TCM is not present and if the DTCM bit is 1 Data TCM is present If the ITCM bit is 0 ...

Page 27: ...M926ES J Subsystem in the device also includes the Embedded Trace Buffer ETB The ETM consists of two parts the trace port and triggering facilities The two ETM parts are shown in Table 3 5 Note The device trace port is not pinned out Instead it is connected to a 4KB Embedded Trace Buffer ETB enabled debug tools are required to read interpret the captured trace data Table 3 5 ETM Part Descriptions ...

Page 28: ...h a narrow trace port An external Trace Port Analyzer TPA is used to capture the trace information Note See Chapter 10 of the Embedded Trace Macro cell Support of the ARM926EJ S TRM downloadable from http www arm com for more detailed information ARM Core 28 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 29: ...1 4000 0x0001 7FFF 16K ARM RAM1 Data ARM RAM1 ARM RAM1 0x0001 8000 0x0001 FFFF 32K ARM ROM Data ARM ROM ARM ROM only 8K used 0x0002 0000 0x000F FFFF 896K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x...

Page 30: ... following external memories DDR2 mDDR Synchronous DRAM Asynchronous EMIF OneNand NAND Flash External host devices Additionally the ARM has access to the various common media storage card interfaces The ARM and EDMA have access to the registers and memories of the following peripherals see Table 4 2 EDMA Controller Three UARTs I2C Inter IC Communication Three 64 bit timers each configurable as one...

Page 31: ...p Controller 0x01C4 1000 0x01C4 1FFF 4K Reserved 0x01C4 2000 0x01C4 7FFF 24K ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K Reserved 0x01C4 8400 0x01C6 3FFF 111K USB OTG 2 0 Regs RAM 0x01C6 4000 0x01C6 5FFF 8K SPI0 0x01C6 6000 0x01C6 67FF 2K SPI1 0x01C6 6800 0x01C6 6FFF 2K GPIO 0x01C6 7000 0x01C6 77FF 2K SPI2 0x01C6 7800 0x01C6 FFFF 2K VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K VPSS Clock Con...

Page 32: ...000 0x01E1 0FFF 4K Multimedia SD 0 0x01E1 1000 0x01E1 FFFF 60K Reserved 0x01E2 0000 0x01FF FFFF 1792K ASYNC EMIF Data CE0 0x0200 0000 0x03FF FFFF 32M ASYNC EMIF Data CE1 0x0400 0000 0x05FF FFFF 32M Reserved 0x0600 0000 0x09FF FFFF 64M Reserved 0x0A00 0000 0x0BFF FFFF 32M Reserved 0x0C00 0000 0x0FFF FFFF 64M Memory Mapping 32 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 33: ...termediate buffering for processing resizing of image data in the VPFE Numerous OSD display buffers Intermediate buffering for large raw Bayer data image files while performing still camera processing functions Buffering for intermediate data while performing video encode and decode functions Storage of executable firmware for the ARM The external memory interface EMIF provides an 8 bit or 16 bit ...

Page 34: ...mory cards ARM ROM supports booting of the device ARM processor from NAND Flash located at CE0 The OneNAND mode supports the following features OneNAND Flash on up to two chip selects Supports only 16 bit data bus widths Supports asynchronous writes and reads Supports synchronous reads with continuous linear burst mode Does not support synchronous reads with wrap burst modes Programmable cycle tim...

Page 35: ...wo separate PLL controllers PLLC1 and PLLC2 PLLC1 generates the clocks required by the ARM VPBE VPSS and peripherals PLL2 generates the clock required by the DDR PHY A block diagram of the clocking architecture is shown in Figure 5 1 The PLLs are described further in Chapter 6 Note Refer to the device specific data manual for information on supported device clocking configurations e g supported PL...

Page 36: ...Overview www ti com Figure 5 1 Clocking Architecture Device Clocking 36 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 37: ...the TMS320DM335 Digital Media System on Chip DMSoC Video Processing Back End VPBE Reference Guide SPRUFX9 The USB Controller is driven by two clocks an output clock of PLL1 and an output clock of the USB Phy The USB Phy clock is configurable by the USB Phy clock source bits PHYCLKSRC in the USB Phy control register USB_PHY_CTL in the System Control Module USBPHY_CTL is described in Chapter 9 When ...

Page 38: ...ons on changing PLL settings Domain clocks alignment Clock gating PLL bypass PLL power down The various clock outputs given by the PLL controller are as follows Domain clocks SYSCLKn Bypass domain clock SYSCLKBP Auxiliary clock from reference clock AUXCLK Various dividers that can be used are as follows Pre PLL divider PREDIV Post PLL divider POSTDIV SYSCLK divider PLLDIV1 PLLDIVn SYSCLKBP divider...

Page 39: ...SYSCLK4 divider value is programmable program to 4 or 2 See the data manual for all supported configurations SYSCLKBP divider value is fixed to 3 SYSCLK1 is routed to the ARM Subsystem SYSCLK2 is routed to peripherals SYSCLK3 is routed to the VPBE module SYSCLK4 is routed to the VPSS module AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1 SYSCLKBP is route...

Page 40: ...tor input same input as PLLC1 PLL pre divider value is programmable PLL multiplier value is programmable PLL post divider value is fixed to 1 Only SYSCLK 1 is used SYSCLK1 divider value is fixed to 1 SYSCLKBP divider value is fixed to 8 SYSCLK1 is routed to the DDR PHY SYSCLKBP is routed to the output pin CLKOUT3 AUXCLK is not used Table 6 2 PLLC2 Output Clocks Output Clock Used by PLLDIV Divider ...

Page 41: ...bled and PLLM PREDIV POSTDIV and the PLL are used when PLLEN 0 bypass mode is enabled and PLLM PREDIV POSTDIV and the PLL are bypassed When bypass mode is enabled the input reference clock is directly input to the system clock dividers PLLDIVn The PLL controller defaults after reset to bypass mode When in PLL mode PLLEN 1 the input reference clock is supplied to divider PREDIV Divider PREDIV must ...

Page 42: ... and multiplier values 10 If necessary write PLLDIV to set PLLDIVn dividers Note that you must apply the GO operation to change these dividers to new ratios See Section 6 5 2 1 11 Wait at least 5 miro seconds for the PLL reset 12 In PLLCTL write PLLRST 0 de assert PLL reset 13 Wait at least 8000 reference clock cycles for the PLL to lock 14 In PLLCTL write PLLEN 1 to switch from bypass mode to PLL...

Page 43: ...ted SYSCLKn toggles at the rate programmed in the RATIO field in PLLDIVn Any SYSCLKn with the corresponding ALNn bit in ALNCTL cleared to 0 remains free running during a GO operation SYSCLKn is not modified to the new RATIO rate in PLLDIVn SYSCLKn is not aligned to other SYSCLKs Do not program any ALNn bit in ALNCTL to 0 always program ALNCTL so that all SYSCLKs are aligned The GOSTAT bit in PLLST...

Page 44: ...PLL 1 In PLLCTL write PLLEN 0 bypass mode 2 Wait at least 4 reference clock cycles for the PLLEN mux to change 3 In PLLCTL write PLLPWRDN 1 to power down the PLL To wakeup the PLL from its power down mode follow the PLL sequence described in Section 6 5 1 1 Table 6 3 lists the base address for the PLLC1 and PLLC2 registers Table 6 4 lists the memory mapped registers for PLLC1 and PLLC2 Also see th...

Page 45: ...SCLKn divider ratio change and align control register Section 6 6 13 144h DCHANGE PLL divider ratio change status register Section 6 6 14 148h CKEN Clock enable control AUXCLK Section 6 6 15 14Ch CKSTAT Clock status for SYSCLKBP and AUXCLK Section 6 6 16 150h SYSTAT Clock status for SYSCLKn clocks Section 6 6 17 160h PLLDIV4 Divider 4 control divider for SYSCLK4 Section 6 6 18 SPRUFX7 July 2008 PL...

Page 46: ...t description figures throughout this section Figure 6 4 Peripheral ID Register PID 31 24 23 16 15 8 7 0 Reserved TYPE CLASS REV R 0 R 1 R 8 R 2 LEGEND R Read W Write n value at reset Table 6 5 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 TYPE 0 FFh Peripheral Type 0x01 to identify as PLLC 15 8 CLASS 0 FFh Peripheral Class 0x08 7 0 REV 0...

Page 47: ...nd PLLC2 0 Internal oscillator 1 CLKIN square wave 7 PLLSELB Selects PLL A versus PLL B 0 PLL A is selected PLL B is put in power down pll_b_pwrdn_po 1 1 PLL B is selected PLL A is put in power down pll_a_pwrdn_po 1 6 Reserved 0 Reserved 5 PLLENSRC PLL enable source This bit must be cleared to 0 before PLLCTL PLLEN will have any effect 0 PLL enable is controlled by the register bit PLLCTL PLLEN 1 ...

Page 48: ...e default multiplier value is 92 You may change the multiplier value from 92 to 184 Figure 6 6 PLL Multiplier Control Register PLLM 31 8 7 0 Reserved PLLM R 0 R W 179 LEGEND R Read W Write n value at reset Table 6 7 PLL Multiplier Control Register PLLM Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 PLLM 5Bh PLL Multiplier Multiplier value PLLM 1 B7h PLL Controllers PLL...

Page 49: ...quencies Figure 6 7 PLL Pre Divider Control Register PREDIV 31 16 15 14 5 4 0 Reserved PREDEN Reserved RATIO R 0 R 1 R 0 R 7 LEGEND R W Read Write R Read only n value after reset Table 6 8 PLL Pre Divider Control PREDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 PREDEN Pre divider enable For PLLC1 and PLLC2 this bit must always be set to 1 0 Disable 1 Enable 14 5 R...

Page 50: ...abled bit D1EN 1 Figure 6 8 PLL Controller Divider 1 Register PLLDIV1 31 16 15 14 5 4 0 Reserved D1EN Reserved RATIO R 0 R W 1 R 0 R 1 LEGEND R W Read Write R Read only n value after reset Table 6 9 PLL Controller Divider 1 Register PLLDIV1 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 D1EN Divider enable for SYSCLK1 For PLLC1 this bit must always be set to 1 For PLLC...

Page 51: ...r must always be enabled bit D2EN 1 Figure 6 9 PLL Controller Divider 2 Register PLLDIV2 31 16 15 14 5 4 0 Reserved D2EN Reserved RATIO R 0 R W 1 R 0 R 3 LEGEND R W Read Write R Read only n value after reset Table 6 10 PLL Controller Divider 2 Register PLLDIV2 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 D2EN Divider enable for SYSCLK2 For PLLC1 and PLLC2 this bit mu...

Page 52: ...e to PLLC2 therefore all PLLDIV3 bit fields are reserved for PLLC2 Figure 6 10 PLL Controller Divider 3 Register PLLDIV3 31 16 15 14 5 4 0 Reserved D3EN Reserved RATIO R 0 R W 1 R 0 R W 16 LEGEND R Read only n value after reset Table 6 11 PLL Controller Divider 3 Register PLLDIV3 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 D3EN Divider enable for SYSCLK3 For PLLC1 t...

Page 53: ...t PLL1_POSTDIV such that the post divider is equal to 1 But if DEV_SPEED is 1 or 3 it is not possible to change the post divider from the default value of 2 and thus the frequencies are limited The post divider for PLLC2 is always fixed cannot be changed to 1 Figure 6 11 PLL Post Divider Control Register POSTDIV 31 16 15 14 5 4 0 Reserved POSTDEN Reserved RATIO R 0 R 1 R 0 R 0 LEGEND R Read only n...

Page 54: ...LLC2 the divider must always be enabled bit BPDEN 1 Figure 6 12 Bypass Divider Register BPDIV 31 16 15 14 5 4 0 Reserved BPDEN Reserved RATIO R 0 R W 1 R 0 R 2 LEGEND R W Read Write R Read only n value after reset Table 6 13 Bypass Divider Register BPDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 BPDEN Divider enable for bypass clock This bit must always be set to ...

Page 55: ... after reset Table 6 14 PLL Controller Command Register PLLCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSET GO operation command for SYSCLKn ratio change and or phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 Clear bit Write of 0 clears bit t...

Page 56: ... PLL Controller Status Register PLLSTAT 31 1 0 Reserved GOSTAT R 0 R 0 LEGEND R Read n value at reset Table 6 15 PLL Controller Status PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSTAT GO status 0 GO operation is not in progress SYSCLK divider ratios and or phase alignment are not being changed 1 GO operation is in progress SYSCLK divider ratios and or phase ...

Page 57: ...on 31 8 Reserved 0 Reserved 7 0 ALNn 0 1Fh SYSCLKn divider ratio change and alignment enable Do not change the default values of these fields ALN0 is divider ratio change and alignment enable for SYSCLK1 ALN1 is divider ratio change and alignment enable for SYSCLK2 ALN2 is divider ratio change and alignment enable for SYSCLK3 this bit is reserved for PLLC2 ALN3 is divider ratio change and alignmen...

Page 58: ...t Table 6 17 PLLDIV Ratio Change Status DCHANGE Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 SYSn 0 1Fh SYSCLKn divider ratio has been modified status When SYSn is 1 this bit indicates SYSCLKn ratio will be modified during GO operation SYS0 shows divider ratio has been modified for SYSCLK1 SYS1 shows divider ratio has been modified for SYSCLK2 SYS2 shows divider rati...

Page 59: ...es not use the auxiliary clock so the CKEN register is not applicable to PLLC2 and all CKEN bit fields are reserved for PLLC2 Figure 6 17 Clock Enable Control Register CKEN 31 1 0 Reserved AUXEN R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 6 18 Clock Enable Control Register CKEN Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 AUXEN Auxiliary clock...

Page 60: ...LLC2 Figure 6 18 Clock Status Register CKSTAT 31 4 3 2 1 0 Reserved BPON Reserved AUXEN R 0 R 1 R 0 R 1 LEGEND R Read n value at reset Table 6 19 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 BPON SYSCLKBP status Shows the clock on off status for SYSCLKBP 0 Bypass clock is off 1 Bypass clock is on 2 1 Reserved 0 Reserved 0 AUXEN AUXCLK statu...

Page 61: ...le 6 20 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 SYSONn 0 1Fh SYSCLKn status Shows the clock on off status for SYSCLKn SYSON0 shows clock on off status for SYSCLK1 SYSON1 shows clock on off status for SYSCLK2 SYSON2 shows clock on off status for SYSCLK3 this bit is reserved for PLLC2 SYSON3 shows clock on off status for SYSCLK4 this ...

Page 62: ...ot applicable to PLLC2 therefore all PLLDIV4 bit fields are reserved for PLLC2 Figure 6 20 PLL Controller Divider 4 Register PLLDIV4 31 16 15 14 5 4 0 Reserved D4EN Reserved RATIO R 0 R W 0 R 0 R W 3 LEGEND R W Read Write R Read n value at reset Table 6 21 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 D4EN Divider enable for S...

Page 63: ...ON OFF Control module resets Supports IcePick emulation features power clock and reset Figure 7 1 Power and Sleep Controller PSC The DM335 system includes one power domain and forty one separate modules as shown in Figure 7 2 and summarized in Table 7 1 The device s power domain is always on when the chip is on and it is referred to as the AlwaysOn power domain The AlwaysOn domain is powered by th...

Page 64: ...Power Domain and Module Topology www ti com Figure 7 2 Power Domain and Module Topology 64 Power and Sleep Controller SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 65: ...nable OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 15 MMC SD0 AlwaysOn ON BTSEL 1 0 00 SyncRst NAND BTSEL 1 0 01 SyncRst OneNAND BTSEL 1 0 10 Enable MMC SD BTSEL 1 0 11 SyncRst UART 16 Reserved Reserved Reserved Reserved 17 ASP AlwaysOn ON SyncRst 18 I2C AlwaysOn ON SyncRst 19 UART0 AlwaysOn ON BTSEL 1 0 00 SyncRst NAND BTSEL 1 0 01 SyncRst OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL...

Page 66: ... OFF power to the power domain is off In the device system the AlwaysOn Power Domain is always in the ON state when the chip is powered on A module can be in one of four states Disable Enable SwRstDisable or SyncReset These four states correspond to combinations of module reset asserted or de asserted and module clock on or off as shown in Table 7 2 Note Reset of a module is defined to completely ...

Page 67: ...ition is automatically handled by the hardware This section describes the procedure for transitioning the module state The procedure for module state transitions is as follows x corresponds to the module Wait for the GOSTATx bit in PTSTAT to clear to 0x0 You must wait for any previously initiated transitions to finish before initiating a new transition Set the NEXT bit in MDCTL x to SwRstDisable 0...

Page 68: ...r Domain Emulation Event Module State Emulation Event Module Local Reset Emulation Event External Power Control Pending Event These interrupt events are summarized in Table 7 4 and described in more detail in this section Table 7 4 PSC Interrupt Events Interrupt Enable Bits Interrupt Condition Control Register Status Bit PDCTLx EMUIHB Interrupt occurs when the emulation alters the power domain sta...

Page 69: ...able bits are the EMUIHB bit in PDCTLx the EMUIHB bit in MDCTL x the EMURSTIE bit in MDCTL x and the EPx bit in EPCPR Note To interrupt the ARM the ARM s power and sleep controller interrupt PSCINT must also be enabled in the ARM interrupt controller See Chapter 8 for more information on the ARM s power and sleep controller interrupt and the ARM interrupt controller The PSC interrupt status bits a...

Page 70: ...nterrupt controller See Chapter 8 for more information The ARM enters the interrupt service routine ISR when it receives the interrupt 1 Read the Px bit in PERRPR the Mx bit in MERRPR0 the Mx bit in MERRPR1 and or the EP bit in EPCPR to determine the source of the interrupt s 2 For each active event that you want to service Read the event status bits in PDSTATx and MDSTAT x depending on the status...

Page 71: ...Register 1 Section 7 7 4 50h MERRCR0 Module Error Clear Register 0 Section 7 7 5 54h MERRCR1 Module Error Clear Register 1 Section 7 7 6 60h PERRPR Power Error Pending Register Section 7 7 7 68h PERRCR Power Error Clear Register Section 7 7 8 70h EPCPR External Power Error Pending Register Section 7 7 9 78h EPCCR External Power Control Clear Register Section 7 7 10 120h PTCMD Power Domain Transiti...

Page 72: ...0 RTL MAJOR CUSTOM MINOR R 0 R 1 R 0 R 5 LEGEND R W Read Write R Read n value at reset Table 7 6 Peripheral Revision and Class Information Register PID Field Descriptions Bit Field Value Description 31 30 SCHEME 0 3h Scheme 29 28 Reserved 0 Reserved 27 16 FUNC 0 FFFh Software compatible 15 11 RTL 0 1Fh RTL Version 10 8 MAJOR 0 7h Major Revision 7 6 CUSTOM 0 3h Indicates a special version for a par...

Page 73: ...Register INTEVAL 31 1 0 Reserved ALLEV R 0 W 0 LEGEND R Read W Write n value at reset Table 7 7 Interrupt Evaluation Register INTEVAL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 ALLEV Re evaluate PSC interrupt 0 A write of 0 has no effect 1 Write 1 to re evaluate the interrupt condition SPRUFX7 July 2008 Power and Sleep Controller 73 Submit Documentation Feedback ...

Page 74: ...or Pending Register 0 mod 0 31 MERRPR0 31 0 M0 32 R 0 LEGEND R Read n value at reset Table 7 8 Module Error Pending Register 0 mod 0 31 MERRPR0 Field Descriptions Bit Field Value Description 31 0 M0 32 Module interrupt status bit for modules 0 31 0 Power domain interrupt is not active 1 Power domain interrupt is active Power and Sleep Controller 74 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 75: ...RRPR1 31 16 Reserved R 0 R 0 15 9 8 0 Reserved M 9 R 0 R 0 LEGEND R W Read Write R Read n value at reset Table 7 9 Module Error Pending Register 1 mod 32 41 MERRPR1 Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 0 M 9 Module interrupt status bit for modules 32 41 0 Power domain interrupt is not active 1 Power domain interrupt is active SPRUFX7 July 2008 Power and Sleep C...

Page 76: ...0 31 0 M0 32 R 0 LEGEND R Read n value at reset Table 7 10 Module Error Clear Register 0 mod 0 31 MERRCR0 Field Descriptions Bit Field Value Description 31 0 M 32 Clears the interrupt bit set in the corresponding MERRPRO register bit field and the MDSTAT interrupt bit fields This pertains to modules 0 31 0 A write of 0 has no effect 1 Clears module interrupt Power and Sleep Controller 76 SPRUFX7 J...

Page 77: ...rved M 9 R 0 R 0 LEGEND R W Read Write R Read n value at reset Table 7 11 Module Error Clear Register 1 mod 32 41 MERRCR1 Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 0 M 9 Clears the interrupt bit set in the corresponding MERRPR1 register bit field and the MDSTAT interrupt bit fields This pertains to modules 32 41 0 A write of 0 has no effect 1 Clears module interrupt...

Page 78: ...ding Register PERRPR 31 1 0 Reserved P 1 R 0 R 0 LEGEND R Read n value at reset Table 7 12 Power Error Pending Register PERRPR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 P 1 Power domain interrupt status 0 Power domain interrupt is not active 1 Power domain interrupt is active Power and Sleep Controller 78 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 79: ...r Register PERRCR 31 1 0 Reserved P 1 R 0 W 0 LEGEND R Read W Write n value at reset Table 7 13 Power Error Clear Register PERRCR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 P 1 Clears the power domain interrupt 0 A write of 0 has no effect 1 Clears the power domain interrupt SPRUFX7 July 2008 Power and Sleep Controller 79 Submit Documentation Feedback ...

Page 80: ...ue at reset Table 7 14 External Power Control Pending Register EPCPR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 EPC 1 External power control pending bit The PSC sets this bit indicating it is ready for an external controller to apply power to the external power pins of the power domain 0 The PSC is not requesting external power control 1 The PSC requests external pow...

Page 81: ...l Clear Register EPCCR 31 1 0 Reserved EPC 1 R 0 W 0 LEGEND R Read W Write n value at reset Table 7 15 External Power Control Clear Register EPCCR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 EPC 1 External power control clear bit 0 A write of 0 has no effect 1 Set this bit to clear the EPCPR interrupt SPRUFX7 July 2008 Power and Sleep Controller 81 Submit Documentatio...

Page 82: ...D R Read W Write n value at reset Table 7 16 Power Domain Transition Command Register PTCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GO 1 Power domain GO transition command 0 A write of 0 has no effect 1 Writing 1 causes the state transition interrupt generation block to evaluate the new PTNEXT and the NEXT states in MDCTL as the desired states of the application P...

Page 83: ...ed GOSTAT 1 R 0 R 0 LEGEND R Read n value at reset Table 7 17 Power Domain Transition Status Register PTSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSTAT 1 Power domain transition status 0 No transition in progress 1 Power domain is transitioning i e either the power domain is transitioning or modules in this power domain are transitioning SPRUFX7 July 2008 Powe...

Page 84: ...lue Description 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active 1 Interrupt is active 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Domain Power_On_Reset POR status This bit reflects the POR status for this power domain including all modules in the domain 0 Power doma...

Page 85: ...15 10 9 8 7 1 0 Reserved EMUIHBIE EPCGOOD Reserved NEXT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read n value at reset Table 7 19 Power Domain Control n Register PDCTLn Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 EMUIHBIE Emulation alters power domain state interrupt enable 0 Disable interrupt 1 Enable interrupt 8 EPCGOOD External power control power good in...

Page 86: ...rrupt active 16 EMURST Emulation alters module reset interrupt active 0 Interrupt not active 1 Interrupt active 15 13 Reserved 0 Reserved 12 MCKOUT Module clock output status Shows status of module clock ON OFF 0 Module clock is off 1 Module clock is on 11 MRSTDONE Module reset done Software is responsible for checking that mode reset is done before accessing the module 0 Module reset is not done ...

Page 87: ... 0 27 40 and 41 Figure 7 18 Module Control n Register 0 41 MDCTLn 31 16 Reserved R 0 15 11 10 9 8 5 4 0 Reserved EMUIHBIE EMURSTIE Reserved NEXT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read n value at reset Table 7 21 Module Control n Register 0 51 MDCTLn Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 EMUIHBIE Interrupt enable for emulation alters module stat...

Page 88: ... interrupt routine can read the ENTRY register and jump to the corresponding ISR directly Thus the ARM does not require a software dispatcher to determine the asserted interrupt The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the ARM Each interrupt is also assigned one of 8 priority levels 2 for FIQ 6 for IRQ For interrupts with the same priority lev...

Page 89: ...imer3 TINT34 54 GPIOBNK0 GPIO 23 SDIOINT0 MMC SD0 55 GPIOBNK1 GPIO 24 MBXINT0 or ASP0 or 56 GPIOBNK2 GPIO MBXINT1 ASP1 25 MBRINT0 or ASP0 or 57 GPIOBNK3 GPIO MBRINT1 ASP1 26 MMCINT0 MMC SD0 58 GPIOBNK4 GPIO 27 MMCINT1 MMC SC1 59 GPIOBNK5 GPIO 28 PWMINT3 PWM3 60 GPIOBNK6 GPIO 29 DDRINT DDR EMIF 61 COMMTX ARMSS 30 AEMIFINT Async EMIF 62 COMMRX ARMSS 31 SDIOINT1 SDIO1 63 EMUINT E2ICE INTC methodology...

Page 90: ...rrupt events Each event causes an IRQ or FIQ to generate only if the corresponding EINT bit enables it The EINT bit enables or disables the event regardless of whether it is mapped to IRQ or to FIQ The IRQ FIQ register always captures each event regardless of whether the interrupt is actually enabled Event priority is determined using both a fixed and a programmable prioritization scheme The AINTC...

Page 91: ... the ARM reads the register They may also change immediately after a read by the ARM if a higher priority event occurs If no IRQ mapped effective interrupt is pending then the IRQENTRY value reflects the EABASE value Similarly if no FIQ mapped effective interrupt is pending then the FIQENTRY value reflects the EABASE value 1 For the FIQENTRY If FERAW is 0 FIQENTRY reflects the state of the highest...

Page 92: ...ther interrupts are pending then the IRQz FIQz output to the ARM may also go inactive Enabling the interrupt if it is already pending takes immediate affect This is shown in Figure 8 3 Figure 8 3 Immediate Interrupt Disable Enable If IDMODE is 1 then the EINT effect is delayed Essentially the active interrupt status is latched until cleared by the ARM If EINT is cleared the prioritizer continues t...

Page 93: ...TRY Entry Address 28 0 for valid IRQ interrupt Section 8 4 6 18h EINT0 Interrupt Enable Register 0 Section 8 4 7 1Ch EINT1 Interrupt Enable Register 1 Section 8 4 8 20h INTCTL Interrupt Operation Control Register Section 8 4 9 24h EABASE Interrupt Entry Table Base Address Section 8 4 10 30h INTPRI0 Interrupt 0 7 Priority select Section 8 4 11 34h INTPRI1 Interrupt 8 15 Priority select Section 8 4 ...

Page 94: ...5 Interrupt Status of INT 31 0 if mapped to FIQ 31 0 FIQ 31 0 R W 1 LEGEND R W Read Write n value at reset Table 8 3 Interrupt Status of INT 31 0 if mapped to FIQ Field Descriptions Bit Field Value Description 31 0 FIQ 31 0 Interrupt status of INTx if mapped to FIQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt Interrupt Controller 94 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 95: ...Interrupt Status of INT 63 32 if mapped to FIQ 31 0 FIQ 63 32 R W 1 LEGEND R W Read Write n value at reset Table 8 4 Interrupt Status of INT 63 32 if mapped to FIQ Field Descriptions Bit Field Value Description 31 0 FIQ 63 32 Interrupt status of INTx if mapped to FIQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt SPRUFX7 July 2008 Interrupt Controller 95 Submit Documentation Feedback ...

Page 96: ...errupt Status of INT 31 0 if mapped to IRQ 31 0 IRQ 31 0 R W 1 LEGEND R W Read Write n value at reset Table 8 5 Interrupt Status of INT 31 0 if mapped to IRQ Field Descriptions Bit Field Value Description 31 1 IRQ 31 0 Interrupt status of INTx if mapped to IRQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt Interrupt Controller 96 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 97: ...nterrupt Status of INT 31 0 if mapped to IRQ 31 0 IRQ 63 32 R W 1 LEGEND R W Read Write n value at reset Table 8 6 Interrupt Status of INT 31 0 if mapped to IRQ Field Descriptions Bit Field Value Description 31 0 IRQ Interrupt status of INTx if mapped to IRQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt SPRUFX7 July 2008 Interrupt Controller 97 Submit Documentation Feedback ...

Page 98: ... Figure 8 9 Fast Interrupt Request Entry Address Register FIQENTRY 31 0 FIQENTRY R 0 LEGEND R Read only n value at reset Table 8 7 Fast Interrupt Request Entry Address Register FIQENTRY Field Descriptions Bit Field Value Description 31 0 FIQENTRY 0 FFFF FFFFh Interrupt entry table address of the current highest priority FIQ Interrupt Controller 98 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 99: ... Figure 8 10 Interrupt Request Entry Address Register IRQENTRY 31 0 IRQENTRY R 0 LEGEND R Read only n value at reset Table 8 8 Interrupt Request Entry Address Register IRQENTRY Field Descriptions Bit Field Value Description 31 0 IRQENTRY 0 FFFF FFFFh Interrupt entry table address of the current highest priority IRQ SPRUFX7 July 2008 Interrupt Controller 99 Submit Documentation Feedback ...

Page 100: ... 8 9 Figure 8 11 Interrupt Enable Register 0 EINT0 31 0 EINT 31 0 R W 0 LEGEND R W Read Write n value at reset Table 8 9 Interrupt Enable Register 0 EINT0 Field Descriptions Bit Field Value Description 31 0 EINT 31 0 Interrupt enable for INTx 0 Mask interrupt 1 Enable interrupt Interrupt Controller 100 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 101: ... 10 Figure 8 12 Interrupt Enable Register 1 EINT1 31 0 EINT 63 32 R W 0 LEGEND R W Read Write n value at reset Table 8 10 Interrupt Enable Register 1 EINT1 Field Descriptions Bit Field Value Description 31 0 EINT 63 32 Interrupt enable for INTx 0 Mask interrupt 1 Enable interrupt SPRUFX7 July 2008 Interrupt Controller 101 Submit Documentation Feedback ...

Page 102: ...R W Read Write R Read only n value at reset Table 8 11 Interrupt Operation Control Register INTCTL Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 IDMODE Interrupt disable mode 0 Disable immediately 1 Disable after ack 1 IERAW Masked interrupt reflected in the IRQENTRY register 0 Disable reflect 1 Enable reflect 0 FERAW Masked interrupt reflect in FIQENTRY register 0 Disa...

Page 103: ... R W Read Write R Read only n value at reset Table 8 12 EABASE Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reserved 28 3 EABASE 0 3FF FFFFh Interrupt entry table base address 8 byte aligned 2 Reserved 0 Reserved 1 0 SIZE Size of each entry in the interrupt entry table 0 4 bytes 1h 8 bytes 2h 16 bytes 3h 32 bytes SPRUFX7 July 2008 Interrupt Controller 103 Submit Documentation Fe...

Page 104: ...e at reset Table 8 13 Interrupt Priority Register 0 INTPRI0 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT7 0 7h Selects INT7 priority level 27 Reserved 0 Reserved 26 24 INT6 0 7h Selects INT6 priority level 23 Reserved 0 Reserved 22 20 INT5 0 7h Selects INT5 priority level 19 Reserved 0 Reserved 18 16 INT4 0 7h Selects INT4 priority level 15 Reserved 0 Reserved 14...

Page 105: ...t reset Table 8 14 Interrupt Priority Register 1 INTPRI1 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT15 0 7h Selects INT15 priority level 27 Reserved 0 Reserved 26 24 INT14 0 7h Selects INT14 priority level 23 Reserved 0 Reserved 22 20 INT13 0 7h Selects INT13 priority level 19 Reserved 0 Reserved 18 16 INT12 0 7h Selects INT12 priority level 15 Reserved 0 Reserv...

Page 106: ... reset Table 8 15 Interrupt Priority Register 2 INTPRI2 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT23 0 7h Selects INT23 priority level 27 Reserved 0 Reserved 26 24 INT22 0 7h Selects INT22 priority level 23 Reserved 0 Reserved 22 20 INT21 0 7h Selects INT21 priority level 19 Reserved 0 Reserved 18 16 INT20 0 7h Selects INT20 priority level 15 Reserved 0 Reserve...

Page 107: ... reset Table 8 16 Interrupt Priority Register 3 INTPRI3 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT31 0 7h Selects INT31 priority level 27 Reserved 0 Reserved 26 24 INT30 0 7h Selects INT30 priority level 23 Reserved 0 Reserved 22 20 INT29 0 7h Selects INT29 priority level 19 Reserved 0 Reserved 18 16 INT28 0 7h Selects INT28 priority level 15 Reserved 0 Reserve...

Page 108: ... reset Table 8 17 Interrupt Priority Register 4 INTPRI4 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT39 0 7h Selects INT39 priority level 27 Reserved 0 Reserved 26 24 INT38 0 7h Selects INT38 priority level 23 Reserved 0 Reserved 22 20 INT37 0 7h Selects INT37 priority level 19 Reserved 0 Reserved 18 16 INT36 0 7h Selects INT36 priority level 15 Reserved 0 Reserve...

Page 109: ... reset Table 8 18 Interrupt Priority Register 5 INTPRI5 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT47 0 7h Selects INT47 priority level 27 Reserved 0 Reserved 26 24 INT46 0 7h Selects INT46 priority level 23 Reserved 0 Reserved 22 20 INT45 0 7h Selects INT45 priority level 19 Reserved 0 Reserved 18 16 INT44 0 7h Selects INT44 priority level 15 Reserved 0 Reserve...

Page 110: ... reset Table 8 19 Interrupt Priority Register 6 INTPRI6 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT55 0 7h Selects INT55 priority level 27 Reserved 0 Reserved 26 24 INT54 0 7h Selects INT54 priority level 23 Reserved 0 Reserved 22 20 INT53 0 7h Selects INT53 priority level 19 Reserved 0 Reserved 18 16 INT52 0 7h Selects INT52 priority level 15 Reserved 0 Reserve...

Page 111: ... reset Table 8 20 Interrupt Priority Register 7 INTPRI7 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 28 INT63 0 7h Selects INT63 priority level 27 Reserved 0 Reserved 26 24 INT62 0 7h Selects INT62 priority level 23 Reserved 0 Reserved 22 20 INT61 0 7h Selects INT61 priority level 19 Reserved 0 Reserved 18 16 INT60 0 7h Selects INT60 priority level 15 Reserved 0 Reserve...

Page 112: ...Management Deep Sleep Control Bandwidth Management Bus master DMA priority control This chapter describes the system control module The DEVICE_ID register of the System Control Module contains a software readable version of the JTAG ID device Software can use this register to determine the version of the device on which it is executing The register format and description are shown in Table 9 11 an...

Page 113: ...2 with descriptions in Table 9 5 The PINMUX2 register controls pin multiplexing for the AEMIF pins The register format is shown in Figure 9 3 A brief description of each field is shown in Table 9 6 The PINMUX3 register controls pin multiplexing for the GIO pins The register format is shown in Figure 9 4 A brief description of each field is shown in Table 9 7 The PINMUX4 register controls pin multi...

Page 114: ... out pins CLKOUT 3 1 The purpose of these pins is to provide input clock to external components which are CCD clock to the AFE TG audio clock and clock for motor control The CCD clock is the input crystal clock fed undivided directly to the pin CLKOUT1 the audio clock is a divide by 3 clock CLKOUT2 and the motor control is a divide by 8 clock CLKOUT3 The register CLKOUT is the CLK_OUT 3 1 divisor ...

Page 115: ...er ID for each device master is shown in Table 9 1 Table 9 1 Master IDs MSTID Master 0 ARM Instruction 1 ARM Data 2 Reserved 3 Reserved 4 7 Reserved 8 VPSS 9 Reserved 10 EDMA 11 15 Reserved 16 EDMA Channel 0 read 17 EDMA Channel 0 write 18 EDMA Channel 1 read 19 EDMA Channel 1 write 20 31 Reserved 32 Reserved 33 Reserved 34 USB 35 Reserved 36 Reserved 37 Reserved 38 63 Reserved SPRUFX7 July 2008 S...

Page 116: ...is programmed in the chip level MSTRPRI registers The default priority level for each device bus master is shown in Table 9 2 Application software is expected to modify these values to obtain the desired system performance Table 9 2 Default Master Priorities Master Default Priority VPSS 0 1 EDMA Ch 0 0 EDMA Ch 1 0 ARM DMA 1 ARM CFG 1 Reserved Reserved Reserved Reserved USB 4 Reserved Reserved Rese...

Page 117: ...I control Section 9 10 11 28h DEVICE_ID Device ID Section 9 10 12 2Ch VDAC_CONFIG Video DAC Configuration Section 9 10 13 30h TIMER64_CTL TIMER64_CTL Timer64 Input Control Section 9 10 14 34h USB_PHY_CTRL USB PHY Control Section 9 10 15 38h MISC Miscellaneous Control Section 9 10 16 3Ch MSTPRI0 Master Priorities Reg0 Section 9 10 17 40h MSTPRI1 Master Priorities Reg1 Section 9 10 18 44h VPSS_CLK_C...

Page 118: ... only n value after reset Table 9 4 PINMUX0 Pin Mux 0 Video In Pin Mux Register Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 PCLK Enable the PCLK Video In Pin Mux 0 GIO 82 1 PCLK 13 CAM_WEN Enable the CAM_WEN Video In Pin Mux 0 GIO 83 1 CAM_WEN 12 CAM_VD Enable the CAM_VD Video In Pin Mux 0 GIO 84 1 CAM_VD 11 CAM_HD Enable the CAM_HD Video In Pin Mux 0 GIO 85 1 CAM_H...

Page 119: ...In Pin Mux 0 GIO 98 1 CIN 4 2 SPI 2 _SDI 3 SPI 2 _SDENA 1 5 4 YCIN_5 Enable the CIN 5 Video In Pin Mux 0 GIO 99 1 CIN 5 2 SPI 2 _SDENA 0 3 Reserved 3 2 CIN_6 Enable the CIN 6 Video In Pin Mux 0 GIO 100 1 CIN 6 2 SPI 2 _SDO 3 Reserved 1 0 CIN_7 Enable the CIN 7 Video In Pin Mux 0 GIO 101 1 CIN 7 2 SPI 2 _SCLK 3 Reserved SPRUFX7 July 2008 System Control Module 119 Submit Documentation Feedback ...

Page 120: ...le 9 5 PINMUX1 Pin Mux 1 Video Out Pin Mux Register Field Descriptions Bit Field Value Description 31 23 RESERVED 0 Reserved Must be set to 0 22 VCLK Enable VCLK Video Out Pin Mux 0 VCLK 1 GI0 68 21 20 EXTCLK Enable EXTCLK Video Out Pin Mux 0 GIO 69 1 EXTCLK 2 B2 3 PWM3 19 18 FIELD Enable FIELD Video Out Pin Mux 0 GIO 70 1 FIELD 2 R2 3 PWM3 17 DLCD Enable DLCD Signal Video Out Pin Mux 0 LCD_OE or ...

Page 121: ...3 Enable COUT 3 Video Out Pin Mux 0 GIO 77 1 COUT 3 2 PWM2 3 RTO2 7 6 COUT_4 Enable COUT 4 Video Out Pin Mux 0 GIO 78 1 COUT 4 2 PWM2 3 RTO1 5 4 COUT_5 Enable COUT 5 Video Out Pin Mux 0 GIO 79 1 COUT 5 2 PWM2 3 RTO0 3 2 COUT_6 Enable COUT 6 Video Out Pin Mux 0 GIO 80 1 COUT 6 2 PWM1 3 Reserved 1 0 COUT_7 Enable COUT 7 Video Out Pin Mux 0 GIO 81 1 COUT 7 2 PWM0 3 Reserved SPRUFX7 July 2008 System C...

Page 122: ...W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 9 6 PINMUX2 Pin Mux 2 AEMIF Pin Mux Register Field Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved Must be set to 0 11 EM_CLK Enable EM_CLK AEMIF Pin Mux 0 EM_CLK 1 GIO 31 10 EM_ADV Enable EM_ADV AEMIF Pin Mux 0 EM_ADV Address Valid Detect for OneNAND 1 GIO 32 9 EM_WAIT Enable EM_...

Page 123: ...NMUX2 4 1 AECFG 3 0 0010b i e 16_bit data bus full AEMIF address bus plus EM_A 14 EM_BA1 used as 16_bit address This puts the AEMIF module in Half Rate mode required for OneNAND 0 EM_BA0 Byte address for 8 bit data bus 1 EM_A14 Address MSB required for OneNAND 2 GIO 54 3 Reserved 1 EM_A0_BA1 Enable EM_A0 BA1 AEMIF Pin Mux Reset value set by AECFG 0 sets AEMIF address width for boot OneNAND operati...

Page 124: ... Write n value after reset Table 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reserved 28 GIO7 Enable GIO 7 GPIO Pin Mux 0 GIO 7 1 SPI0_SDENA 1 27 GIO8 Enable GIO 8 GPIO Pin Mux 0 GIO 8 1 SPI1_SDO 26 25 GIO9 Enable GIO 9 GPIO Pin Mux 0 GIO 9 1 SPI0_SDI 2 SPI0_SDENA 1 3 Reserved 24 GIO10 Enable GIO 10 GPIO Pin Mux 0 GIO 10 1 SPI1_SC...

Page 125: ...eserved 11 10 GIO21 Enable GIO 21 GPIO Pin Mux 0 GIO 21 1 SD1_DATA2 2 UART2_CTS 3 Reserved 9 8 GIO22 Enable GIO22 GPIO Pin Mux 0 GIO 22 1 SD1_DATA3 2 UART2_RTS 3 Reserved 7 GIO23 Enable GIO 23 GPIO Pin Mux 0 GIO 23 1 SD1_CMD 6 GIO24 Enable GIO 24 GPIO Pin Mux 0 GIO 24 1 SD1_CLK 5 GIO25 Enable GIO 25 GPIO Pin Mux 0 GIO 25 1 ASP0_FSR 4 GIO26 Enable GIO 26 GPIO Pin Mux 0 GIO 26 1 ASP0_CLKR 3 GIO27 En...

Page 126: ...i com Table 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions continued Bit Field Value Description 0 GIO30 Enable GIO 30 GPIO Pin Mux 0 GIO 30 1 ASP0_DX System Control Module 126 SPRUFX7 July 2008 Submit Documentation Feedback ...

Page 127: ..._SDENA R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value at reset Table 9 8 PINMUX4 Pin Mux 4 Misc Pin Mux Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 MMCSD0_MS Enable MMCSD0_MS 0 MMC SD 0 SD0_CLK SD0_CMD SD0_DATA 3 0 1 Reserved 1 SPI0_SDI Enable SPI0_SDI 0 SPI0_SDI 1 GIO 32 0 SPI0_SDENA Enable SPI0_SDENA0 0 SPI0_SDENA 0 1 GIO 103 SPRUFX7 July 2...

Page 128: ...e compatible with the boot mode OneNAND boot requires AECFG 3 0 0010b Only 8_bit NAND boot is supported AECFG 3 0 1XXXb 0 Boot from ROM NAND Flash boot mode 1 Boot from AEMIF OneNAND 2 Boot from ROM SD0 boot mode 3 Boot from ROM UART0 boot mode 5 4 Reserved 0 Reserved 3 0 OSC_SW 1 2 AEMIF Configuration settings for boot by AECFG 3 0 pins 3 AEMIF Data Bus width 0 16 bit 1 8 bit 2 1 Configuration of...

Page 129: ..._INTMUX ARM Interrupt Mux Control Register Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 INT20 INT20 PSC or Reserved 0 Power Sleep Controller 1 Reserved 6 INT25 INT25 ASP0 RINT or ASP1 RINT 0 ASP0 RINT 1 ASP1 RINT 5 INT24 INT24 ASP0 XINT or ASP1 XINT 0 ASP0 XINT 1 ASP1 XINT 4 INT19 INT19 SPI2_INT0 or EDMA TC1 Error Interrupt 0 SPINT2_0 1 EDMA TC1 Error 3 INT18 INT18 SPI...

Page 130: ...9 EVT8 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 9 11 EDMA_EVTMUX EDMA Event Mux Control Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 EVT26 EVT26 MMC SD 0 Receive 0 MMC SD 0 Receive Event 1 Reserved 1 EVT9 EVT9 ASP1 Receive or Timer2 TINT5 0 ASP1 Receive Event 1 TIMER2 TINT5 0 EVT8 EVT9 ASP1 transmit or Timer2 TINT4 0 AS...

Page 131: ... 0 15 4 3 2 1 0 Reserved DDRDATA_SLEW DDRCMD_SLEW R 0 R 0 R 0 LEGEND R Read only n value after reset Table 9 12 DDR_SLEW DDR Slew Field Descriptions Bit Field Value Description 31 4 RESERVED 0 Reserved 3 2 DDRDATA_SLEW 0 3h DDR data slew programmed in eFuse 1 0 DDRCMD_SLEW 0 3h DDR command slew programmed in eFuse SPRUFX7 July 2008 System Control Module 131 Submit Documentation Feedback ...

Page 132: ...INMUX3 register Figure 9 10 CLKOUT CLKOUT div out Control 31 3 2 1 0 Reserved CRYS_DIV8 CRYS_DIV3 CRYS_DIV1 R 0 R 1 R 1 R 1 LEGEND R Read only n value at reset Table 9 13 CLKOUT CLKOUT div out Control Field Descriptions Bit Field Value Description 31 3 RESERVED 0 Reserved 2 CRYS_DIV8 CLKOUT3 Enable CLKOUT3 is crystal frequency reference clock divided by 8 1 CRYS_DIV3 CLKOUT2 Enable CLKOUT2 is crys...

Page 133: ...NUM MFGR Reserved R 0 R 0xB73B R 0x017 R 1 LEGEND R Read only n value at reset Table 9 14 DEVICE_ID Device ID Field Descriptions Bit Field Value Description 31 28 DEVREV 0 7h Device Revision 27 12 PARTNUM 0 FFFFh Part Number Device JTAG ID Uniquely Defined 11 1 MFGR 0 7FFh Manufacturer s JTAG ID Texas Instruments Mfg ID 0 RESERVED Reserved Always 1 SPRUFX7 July 2008 System Control Module 133 Submi...

Page 134: ... trimming control bit for VREF 25 22 TRESB4R2 0 Fh Resistance trimming control bit for VREF 21 18 TRESB4R1 0 Fh Resistance trimming control bit for VREF 17 11 TRIMBITS 0 7Fh PNP transistor trimming control bit for VREF 10 PWD_BGZ Power Down of VREFF 0 Power down 1 Power up 9 SPEED Faster operation of VREF transfer 0 Normal 1 Faster 8 TVINT TV cable connect status from DAC 0 Cable connected 1 Cable...

Page 135: ...rved GIO3_4 GIO1_2 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value at reset Table 9 16 TIMER64_CTL Timer64 Input Control Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 GIO3_4 GIO3 OR GIO4 for input 0 gio3 for input 1 gio4 for input 0 GIO1_2 GIO1 OR GIO2 for input 0 gio1for input 1 gio2 for input SPRUFX7 July 2008 System Control Module 135 Submit Documentation F...

Page 136: ...0 USB PHY data polarity no inversion 1 USB PHY data polarity inversion 10 9 PHYCLKSRC USB PHY input clock source 0 24MHz directly from crystal 1 12MHz after dividing 36 MHz crystal by 3 2 PLLC1 sysclk3 backup in case 27MHz crystal is used 3 Reserved 8 PHYCLKGD USB PHY Power and Clock Good 0 Phy power not ramped or PLL not locked 1 Phy power is good and PLL is locked 7 SESNDEN Session End Comparato...

Page 137: ...ion 2 VPSS_OSCPDW VPSS oscillator power down control N 0 VPSS MXI2 powered 1 VPSS MXI2 power off 1 OTGPDWN USB OTG analog block power down control 0 OTG analog block powered 1 OTG analog block power off 0 PHYPDWN USB PHY power down control 0 PHY powered 1 PHY power off SPRUFX7 July 2008 System Control Module 137 Submit Documentation Feedback ...

Page 138: ...L1_POSTDIV PLL1 post divider selection 0 Sets PLL1 post divider equal to 1 Setting this bit to 0 has no effect when DEV_SPEED equals 1 or 3 1 Sets PLL1 post divider equal to 2 0 AIM_WAIST ARM Internal Memory Wait States 0 1 wait state to IRAM 1 0 wait state to IRAM Set this bit for zero wait state only if the ARM clock frequency is less than or equal to 150 MHz The MSTPRI0 registers provides contr...

Page 139: ...ers DMA priorities Figure 9 17 Master Priorities 1 MSTPRI1 Register 31 11 10 8 7 0 Reserved USBP Reserved R 0 R W 0x4 R 0 LEGEND R W Read Write R Read only n value at reset Table 9 20 Master Priorities 1 MSTPRI1 Register Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 8 USBP 0 7h USB bus priority 7 0 Reserved 0 Reserved SPRUFX7 July 2008 System Control Module 139 Submit...

Page 140: ...CLK_SRC 27MHz Input Source 0 PLL1 divided down SYSCLK3 1 External crystal 2 MXI2 MXO2 2 External crystal 1 MXI1 MXO1 3 Reserved 4 DACCLKEN Video DAC clock enable 0 disable 1 enable 3 VENCLKEN Video Encoder clock enable 0 disable 1 enable 2 PCLK_INV Invert VPFE pixel clock PCLK 0 VENC clk mux and CCDC receive normal PCLK 1 VENC clk mux and CCDC receive inverted PCLK 1 0 VPSS_MUXSEL VPSS clock selec...

Page 141: ...et to 0 before enabling or initiating Deep Sleep The ARM should 1 Prepare the device system for shutdown by placing DDR in auto_refresh and other powerdown housekeeping as necessary and then 2 Enable Deep Sleep Mode SLEEPENABLE 1 shut down 3 Inform the PMU MCU it is ready for Deep Sleep 4 Go into a loop polling for this SLEEPCOMPLETE bit to be set indicating it can proceed with restarting the DDR ...

Page 142: ...r GIO n Input 31 30 21 20 0 ENABLE Reserved INTERVAL R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value at reset Table 9 23 DEBOUNCE 8 De bounce for GIO n Input Field Descriptions Bit Field Value Description 31 ENABLE Debounce Enable 0 Debounce Enable 1 Debounce Disable 30 21 RESERVED 0 Reserved 20 0 INTERVAL 0 1F FFFFh Interval count for the debounce circuit System Control Module 142 SPRUF...

Page 143: ...rite R Read only n value after reset Table 9 24 VTPIOCR VTP IO Control Field Descriptions Bit Field Value Description 31 16 RESERVED 0 Reserved 15 READY VTP Ready Status 0 VTP not ready 1 VTP ready 14 VTPIOREADY VTP IO Ready Write 1 when VTP IO is ready 0 VTP IO not ready 1 VTP IO ready 13 CLR VTP Clear Write 0 to clear VTP flops 0 Clear VTP 1 Un clear VTP 12 9 RESERVED 0 Reserved 8 PWRSAVE VTP Po...

Page 144: ...tor or Watchdog Timer WDT Same effect as warm reset System Reset ARM emulator Resets all modules except memory and ARM emulation It is a soft reset that maintains memory contents and does not affect or reset clocks or power states Module Reset ARM software Resets a specific module Allows the ARM software to independently reset a module Module reset is intended as a debug tool not as a tool to use ...

Page 145: ...er sequencing and reset timing requirements Warm reset is like POR except the ARM emulation circuitry is not reset Warm reset allows an ARM emulator to initiate chip reset using TRSTN and RESETN while remaining active during and after the reset sequence The following steps describe the warm reset sequence 1 Emulator drives TRSTN high and RESETN low to initiate warm reset 2 Emulator drives RESETN h...

Page 146: ...iates system reset via the ICECrusher emulation module It is considered a soft reset i e memory is not reset None of the following modules are reset DDR EMIF PLL Controller PLLC Power and Sleep Controller PSC and emulation The following steps describe the system reset sequence 1 The emulator initiates system reset 2 The proper modules are reset 3 The system reset finishes the proper modules are re...

Page 147: ...MXI1 typically 24 MHz drives the chip after reset For more information see Chapter 5 and Chapter 6 The default state of the PLLs is reflected by the default state of the register bits in the PLLC registers Only a subset of modules are enabled after reset by default Table 7 1 in Chapter 7 shows which modules are enabled after reset Furthermore as shown in Table 7 1 the following modules are enabled...

Page 148: ...input pins AECFG 3 0 determine the AEMIF configuration immediately after reset Use AECFG 3 0 to properly configure the pins of the AEMIF Refer to the section on pin multiplexing in Chapter 9 When AEMIF is enabled the wait state registers are reset to the slowest possible configuration which is 88 cycles per access 16 cycles of setup 64 cycles of strobe and 8 cycles of hold Thus with a 24 MHz clock...

Page 149: ...1 0 00 ARM NAND Boot BTSEL 1 0 10 ARM MMC SD Boot BTSEL 1 0 11 ARM UART Boot If NAND boot fails then MMC SD mode is tried If MMC SD boot fails then MMC SD boot is tried again If UART boot fails then UART boot is tried again RBL uses GIO61 to indicate boot status can use to blink LED After reset GIO61 is initially driven low e g LED off If NAND boot fails and then MMC SD boot fails then GIO61 shall...

Page 150: ...ot Instead copies a second stage Uwer Boot Loader UBL from MMC SD to ARm Internal RAM AIM and transfers control to the user software Support for MMC SD Native protocol MMC SD SPI protocol is not supported Support for descriptor error detection and retry up to 24 times when loading UBL Support for up to 30KB UBL 32KB 2KB for RBL stack ARM ROM Boot UART mode No support for a full firmware boot Inste...

Page 151: ...s from the BOOTCFG register If the value in BTSEL 1 0 from the BOOTCFG register is 00 the NAND mode executes The outline of operations followed in the NAND mode is described in Figure 11 2 The NAND boot mode assumes the NAND is located on the EM_CE0 interface whose bus configuration is configure by the pins AECFG 3 0 The pins AECFG 3 0 must be configured such that the proper EMIF signals are avail...

Page 152: ...riptor gives the information required for loading and control transfer to the UBL The UBL is then read and processed The RBL may enable any combination of faster EMIF and I Cache operations based on information in the UBL descriptor first Additionally the descriptor provides information on whether or not DMA should be used during UBL copying Once the user specified start up conditions are set the ...

Page 153: ...sent 16 Starting Page of UBL Page number where user boot loader is present Note The first 32 bytes of AIM are the ARM s system interrupt vector table IVT 8 vectors 4 bytes each The UBL copy starts after the 32 byte IVT Different NAND boot mode options can be setting different MAGIC IDs in the UBL descriptor Table 11 2 lists the UBL signatures Table 11 2 UBL Signatures and Special Modes Mode Value ...

Page 154: ...rome3 syndromes10 3 0x03 6 syndromes10 2 0x3F0 4 Syndrome4 syndromes10 3 0x3FC 2 Syndrome5 syndromes10 4 0xFF Syndrome6 syndromes10 5 0x3F 2 syndromes10 4 0x300 8 Syndrome7 syndromes10 6 0x0F 4 syndromes10 5 0x3C0 6 Syndrome8 syndromes10 7 0x03 6 syndromes10 6 0x3F0 4 Syndrome9 syndromes10 7 0x3FC 2 Syndromex Write to NAND flash 8bit Data syndromes10 x Calculated by IP Algorithm to store 10 bit co...

Page 155: ...t Loader magic number in the blocks after CIS IDI page CIS IDI is generally block 0 page 0 See Figure 11 8 Magic number is detected based on reading 0xA1ACEDxx in the first 32 bits of page 0 in a block Only Page 0 of blocks 1 to 24 will be read and searched for the magic number The magic number for all blocks will be read to ascertain that the block is not an invalid block For debug purposes when ...

Page 156: ... the UBL will correct the error via the ECC correction algorithm If the read fails due to any other error the descriptor search process begins anew in the next block after that in which the UBL descriptor was found for up to the first 24 blocks If no valid UBL descriptor is found after searching 24 blocks the RBL will try to boot via MMC SD Give control to User boot loader at UBL Entry Address Fig...

Page 157: ...y point addr of UBL UBL magic number ID 32 bits Starting page of UBL Starting block of UBL 0xA1ACED00 0x00002100 0x00000013 0x00000001 0x00000002 UBL start addr 19 pages Block 1 Page 2 User boot loader UBL definition 0x0000 0x100000 0x0020 0x3FFF 0x13FFF IVT IRAM0 0x4000 0x781F 0x1781F IRAM0 0x14000 0x7FFF 0x17FFF ITCM DTCM Found magic number ROM bootloader copies UBL into IRAM0 Then transfers con...

Page 158: ...AND read error detected If no magic number found or NAND read error detected 11 2 1 2 NAND Device IDs Supported ARM ROM Boot Modes www ti com Figure 11 8 Descriptor Search for ARM NAND Boot Mode The list of IDs supported by ROM boot loader is shown in Table 11 3 with its characteristics Table 11 3 NAND IDs Supported Number of pages per Bytes per page Block shift value Device ID block including ext...

Page 159: ...ive mode All initialization and data transfers are done in native mode SPI mode is not supported After performing the MMC SD initialization sequence the RBL searches for the UBL Descriptor starting in block 0 If a valid UBL is not found in block 0 as determined by reading a proper UBL magic number the next block will be searched Searching will continue for up to 24 blocks This provision for additi...

Page 160: ... UBL including the UBL descriptor If a read error occurs the UBL copy will immediately halt for that instance of magic number but the RBL will continue to search the block following that block in which the magic number was found for another instance of a magic number When a magic number is found the process is repeated Using this retry process the magic number and UBL can be duplicated up to 24 ti...

Page 161: ...igure 11 12 The magic number is of the format 0xA1ACEDxx and is in the first 32 bits of the block CRC error detection shall be enabled when reading the UBL Descriptor If a CRC read error is detected or the magic number is not valid the descriptor search process shall begin anew in the next block after that in which the UBL descriptor was just searched for up to the first 24 blocks When a valid UBL...

Page 162: ...24 When a valid UBL signature is found the corresponding block number M 1 2 3 24 will be written to the last 32 bits of ARM internal memory 0x7FFC Configure the following based on boot descriptor I Cache Starting block of UBL Number of blocks of UBL blocks will be consecutive Entry point address absolute entry point address after loading UBL Copy N consecutive blocks of UBL to AIM until entire UBL...

Page 163: ... UBL UBL magic number ID 32 bits Starting block of UBL 0xA1ACED00 0x00002100 0x00000013 0x00000002 UBL start addr 19 blocks Block 2 User boot loader UBL definition 0x10000 0x13FFF 0x0000 0x3FFF 0x0020 IVT IRAM0 0x781F 0x4000 IRAM1 0x1781F 0x14000 0x7FFF 0x17FFF ITCM DTCM RBL stack space last 32 bits reserved for block number of valid descriptor Found magic number ROM bootloader copies UBL into IRA...

Page 164: ...then the UART boot mode executes This mode enables a small program referred to here as a user boot loader UBL to be downloaded to the on chip ARM internal RAM via the on chip serial UART and executed A host program referred to as serial host utility program manages the interaction with RBL and provides a means for operator feedback and input The UART boot mode execution assumes the following UART ...

Page 165: ...re are three main receive sequences ACK 1KB CRC32 table and user boot loader UBL For each receive sequence a time out check is done in the RBL This means that if a timeout value is reached during the sequence the serial boot mode restarts from the beginning at which the RBL sends out the BOOTME message The error checking behavior for the UART receive mode is the same For each byte received if ther...

Page 166: ...smission The host utility asks you to reset the board UBL Variable The format for UBL is the same as NAND boot The CRC 32 check sum value is calculated for the UBL data and passed by the host serial utility The polynomial used for CRC32 is X 32 X 26 X 23 X 22 X 16 X 12 X 11 X 10 X 8 X 7 X 5 X 4 X 2 X 1 X 0 The RBL expects the data sent from the host utility to be in a particular format This sectio...

Page 167: ...n sending characters from the host to the UART RBL the host utility must insert a delay between each byte character equal to 1 ms Furthermore 5 ms delay must be inserted for each of the timing parameters shown in Figure 11 14 1 The delay time from BOOTME received until ACK sent 2 The delay time from ACK sent to CRC32 table data sent 3 The delay time from CRC32 table data sent to next CRC32 table d...

Page 168: ...ections Table 12 1 Power Management Features Power Management Features Description Clock Management Module clock disable Module clocks can be disabled to reduce switching power Module clock frequency scaling Module clock frequency can be scaled to reduce switching power PLL power down The PLLs can be powered down when not in use to reduce switching power ARM Sleep Mode ARM Wait for Interrupt sleep...

Page 169: ...refore you can use this mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity Furthermore you can power down the PLL when bypassing it to save additional active power Chapter 5 and Chapter 6 describe PLL bypass and PLL power down The ARM module cannot have its clock turned off on via the PSC module like ...

Page 170: ...itiated Deep Sleep and begins polling SLEEPCOMPLETE in DEEPSLEEP During the recovery process the ARM will wake up and detect that SLEEPCOMPLETE has changed The microcontroller transitions GIO0 from high to low and then continues to hold GIO0 low for a minimum of 500 ns until it desires to exit Deep Sleep mode The transition of GIO0 from high to low creates a clock pulse advancing the Deep Sleep st...

Page 171: ... the video signal Furthermore you can use the DACCLKEN in register VPSS_CLK_CTRL to disable each DAC clock See the TMS320DM335 Video Processing Back End VPBE Peripheral Reference Guide SPRUFX9 for detailed information on DAC power down The DDR controller supports self refresh and power down This allows you to put the DDR device in its self refresh or power down states for power savings See the TMS...

Page 172: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...

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