8.4
INTC Registers
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INTC Registers
lists the memory-mapped registers for the INTC. See the device memory map
for the
memory address of these registers.
Table 8-2. Interrupt Controller (INTC) Registers
Offset
Acronym
Register Description
Section
00h
FIQ0
Interrupt Status of INT [31:0] (if mapped to FIQ)
04h
FIQ1
Interrupt Status of INT [63:32] (if mapped to FIQ)
08h
IRQ0
Interrupt Status of INT [31:0] (if mapped to IRQ)
0Ch
IRQ1
Interrupt Status of INT [63:32] (if mapped to IRQ)
10h
FIQENTRY
Entry Address [28:0] for valid FIQ interrupt
14h
IRQENTRY
Entry Address [28:0] for valid IRQ interrupt
18h
EINT0
Interrupt Enable Register 0
1Ch
EINT1
Interrupt Enable Register 1
20h
INTCTL
Interrupt Operation Control Register
24h
EABASE
Interrupt Entry Table Base Address
30h
INTPRI0
Interrupt 0-7 Priority select
34h
INTPRI1
Interrupt 8-15 Priority select
38h
INTPRI2
Interrupt 16-23 Priority select
3Ch
INTPRI3
Interrupt 24-31 Priority select
40h
INTPRI4
Interrupt 32-29 Priority select
44h
INTPRI5
Interrupt 40-47 Priority select
48h
INTPRI6
Interrupt 48-55 Priority select
4Ch
INTPRI7
Interrupt 56-63 Priority select
SPRUFX7 – July 2008
Interrupt Controller
93