9.10.10 DDR_SLEW - DDR Slew
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System Control Register Descriptions
The DDR_SLEW registers allows firmware control of the DDR Slew Rate.
Figure 9-9. DDR_SLEW - DDR Slew
31
16
Reserved
R-0
15
4
3
2
1
0
Reserved
DDRDATA_SLEW
DDRCMD_SLEW
R-0
R-0
R-0
LEGEND: R = Read only; -
n
= value after reset
Table 9-12. DDR_SLEW - DDR Slew Field Descriptions
Bit
Field
Value
Description
31-4
RESERVED
0
Reserved
3-2
DDRDATA_SLEW
0-3h
DDR data slew programmed in eFuse
1-0
DDRCMD_SLEW
0-3h
DDR command slew programmed in eFuse
SPRUFX7 – July 2008
System Control Module
131