Circuit Description
70
CG635 Synthesized Clock Generator
the clock synthesizer. The 20 MHz is also divided down to 10 MHz by U113, a dual
D-type flip-flop. One of the flip-flops, U113A, provides a 10 MHz clock for the
microcontroller, for the GPIB interface controller, and a 10 MHz reference for
phase-locking the 20 MHz timebase to a rear-panel 10 MHz input or to an optional
10 MHz reference oscillator (either an SC10 ovenized oscillator or a PRS10 rubidium
frequency standard.) The differential outputs of the other flip-flop, U113B, drive a
10 MHz tank circuit (T101, 47 pF internal to T101, C126 & C127) and an output filter
(C128, C129, C130 & L104) to provide a rear-panel 10 MHz sine wave output of 1.4 V
pp
amplitude into a 50
ȍ
load via J101.
A rear-panel 10 MHz reference input is applied to a 10 MHz tank circuit (T100, 47 pF
internal to T100 and in parallel with C101) via R100 and C100. The input impedance for
frequencies much higher than 10 MHz is set by R100 (49.9
ȍ
) to provide a high return
loss for high frequency noise. The tank operates as a 2:1 auto-transformer, reducing the
amplitude of 10 MHz input by half and transforming the load (R101) by 4:1, so that the
input impedance is about 1 k
ȍ
at 10 MHz. The output of the tank is applied to U100, an
AD8561 comparator. The comparator’s inverting input is biased to +40 mV by R102 and
R103 so that its non-inverting output is low in the absence of a user-applied 10 MHz
reference input. When a 10 MHz signal is applied to the rear-panel timebase input, the
comparator will generate a TTL square-wave. The low-pass filter (R107/C108) allows
the microcontroller to measure the average value of this square wave via its A/D
converter and so determine the presence of an external 10 MHz reference.
Another comparator (U102) is used to convert the 10 MHz sine wave from an optional
internal timebase (either an SC10 ovenized oscillator or a PRS10 rubidium frequency
standard) into TTL logic levels. The low-pass filter (R109/C109) allows the
microcontroller to measure the average value of this square wave via its A/D converter
and so determine the presence of an optional 10 MHz reference.
The microcontroller will phase lock the 20 MHz timebase to an external 10 MHz
reference if one is supplied (by setting –EXT/OPT and DAC/-PLL low.) If no external
reference is applied, but an optional reference is installed, the microcontroller will phase
lock the 20 MHz timebase to the installed optional 10 MHz reference (by setting
–EXT/OPT high and DAC/–PLL low.) If neither is present, the microcontroller will
provide an analog voltage to the 20 MHz oscillator varactor via a 12-bit DAC to set the
frequency of the 20 MHz timebase per the last calibration (by setting DAC/–PLL high.)
The unused reference is gated “off” near the source (by U101 or U103) to avoid
crosstalk between the references.
The PLL circuit consists of the phase/frequency detector (U106A, U106B and U107), a
pre-filter (R111/C111 & R112/C112), and an integrating loop filter (U109A and
surrounding R’s and C’s). The phase/frequency detector compares the phase of the
selected reference (either external or optional) to the phase of the divided-by-two 20
MHz timebase. If the external (or optional) timebase leads in phase, then the output of
the phase/frequency detector will cause the integrating loop filter to ramp upward,
increasing voltage on the varactor (D100) and so increase the frequency of the 20 MHz
timebase until it is brought in-phase with the selected reference.
Minimum pulse widths will be seen at the Q outputs of U106A/B when the PLL circuit
achieves phase-lock. The pulse widths will be equal to the sum of the propagation delays
through the OR gate (U107, 0.9-3.6 ns) and the flip-flops (U106, 1.0-5.4 ns). Meta-
