Performance Evaluation
49
CG635 Synthesized Clock Generator
2.
Press the Q/Q
¯
Ÿ
and
ź
buttons to select the communication standard under test.
3.
Press ‘SHIFT’, ‘STOP’ to stop the clock outputs at a low level.
4.
Record V
low
as reported by the DVM.
5.
Press ‘SHIFT’, ‘TOGGLE’, ‘SHIFT’ to toggle the clock outputs to a high level.
6.
Record V
high
as reported by the DVM.
The recorded values (V
low
, V
high
) should fall between the minimum and maximum values
listed in Table 19 for each standard level.
Table 19: Minimum and Maximum allowed values for the Q/Q
¯ outputs
Output
Min. (Low, High) V
Measured (Low, High) V
Max. ( Low, High) V
ECL
(–1.828, –1.020)
(–1.772, –0.980)
+7 dBm
(–0.515, 0.485)
(–0.485, 0.515)
LVDS
(1.049, 1.406)
(1.091, 1.454)
PECL 3.3V
(1.475, 2.267)
(1.525, 2.333)
PECL 5V
(3.158, 3.950)
(3.242, 4.050)
To test the Q
¯ output, configure the CG635 as in Figure 4, except swap the connections to
Q and Q
¯ . Repeat the steps above except record V
high
in step 4 and record V
low
in step 6.
CMOS Level Tests
The CMOS output level tests require the setup shown in Figure 5.
Figure 5: CMOS output level test setup
To test the CMOS output, configure the CG635 as follows:
1.
Press ‘SHIFT’, ‘INIT’, ‘Hz’ to return the CG635 to default settings.
2.
Press the CMOS
Ÿ
and
ź
buttons to select the communication standard under
test.
3.
Press ‘SHIFT’, ‘STOP’ to stop the clock outputs at a low level.
4.
Record V
low
as reported by the DVM.
5.
Press ‘SHIFT’, ‘TOGGLE’, ‘SHIFT’ to toggle the clock outputs to a high level.
6.
Record V
high
as reported by the DVM.
The recorded values (V
low
, V
high
) should fall between the minimum and maximum values
listed in Table 20 for each standard level.
Q
Q
CMOS
CG635
Agilent 34401A
6½ Digit DVM
