Circuit Description
86
CG635 Synthesized Clock Generator
switcher is filtered by L2 and C2, to reduce crosstalk between the various supplies in the
system. U1 controls the duty cycle with which it connects the fi24 VDC power
supply to the input of L3 in order to regulate the output voltage to +3.3 VDC. The
flyback diode, D9, turns “on” when U1 disconnects L3 from the +24 V supply. The
output capacitor, C4, holds charge between switching cycles and the L4/C5 filter further
reduces the ripple
The second DC-DC converter (U4) operates at 100 kHz to generate unregulated ±8 VDC
and ±20 VDC. When enabled (by letting go of the soft-start node) the switching
controller drives the gates of the power MOSFETs, Q1 and Q2, with (nearly) 50 % duty
cycle square waves that are 180° out of phase. The MOSFETs drive the primaries of an
ungapped transformer, whose center tap is at +24 VDC. Full wave rectifiers (D3-D10)
drive the inputs to L/C filters (L5-L8 and C12, C15, C18 & C22). The outputs of these
filters are conditioned by linear regulators to provide clean voltages to the instrument.
Ordering diodes on the outputs, D11-D16, assure that load currents will not create
polarity inversions on these power supply outputs.
The DC-DC converters are enabled by the power switch which pulls the –ENABLE line
to ground. Doing so turns off the open collector outputs of U3 releasing the soft start
input to U4 and the ON/-OFF input to U1.
Timebase Options
Schematic sheet “CG_TB1B”
There are two timebase options: an OCXO (SRS p/n SC-10-24-1-J-J-J-J) and a rubidium
frequency standard (SRS p/n PRS10). The optional timebases are held by the same
mechanical bracket and connected to the system using the same adapter PCB.
The adapter PCB schematic is quite simple: J1 is the connector to the OCXO option, J2
is the connector to the rubidium option, and J3 is the connector to the main PCB. The op
amp U1 is used to scale the 0-4.095 VDC frequency calibration voltage (CAL_OPT) to
0-10 VDC for the OCXO or 0-5 VDC for the rubidium. The logic inverter, U2, is used to
invert the logic levels for the RS-232 communication between the microcontroller on the
main PCB and the PRS10 rubidium frequency standard.
Optional PRBS Generator
Schematic sheet “CG_PR1B”
A Pseudo-Random Binary Sequence (PRBS) generator is used for testing data
transmission systems. A typical arrangement is to display an “eye pattern” on an
oscilloscope by triggering the oscilloscope with the clock while displaying the (random)
data after it passes through the data transmission system. An “open” eye pattern is
necessary for reliable data transmission. The eye pattern “closes” from the left and right
with jitter, and from the top and bottom with insufficient channel bandwidth, increasing
the likelihood for transmission errors.
The most common way to create a PRBS generator is to use a linear shift-register,
feeding the input of the shift-register with the exclusive-or of two (particular) data bits as
they shift through the system. The CG635 uses a 7-bit ECL shift register that provides a
