Circuit Description
66
CG635 Synthesized Clock Generator
h.
Compute the FTW for the DDS with 64+ bits of resolution (rounding to the
nearest integer value): FTW = f
O
× D × R × 2
64
/ (f
R
× M × N)
Example
A specific example: Synthesizer parameters to generate 750 MHz.
1.
As 750 MHz lies between 480 MHz and 1024 MHz, using Table 1 we select an
output divider D = 2.
2.
We compute f
VCO
= f
O
× D = 1500 MHz
3.
Enumeration for R & N for f
M
= 19,400,000 Hz is shown in the table below:
R (try)
Nearest N
Required
VCXO(MHz)
VCXO tuning
(ppm)
1 77 19.48051948
4150
2 155 19.35483871
–2328
3 232 19.39655172 –178
4 309 19.41747573 901
5 387 19.37984496
–1039
6 464 19.39655172 –178
7 541 19.40850277 438
8 619 19.38610662 –716
9 696 19.39655172 –178
10 773 19.40491591 253
11 851 19.38895417 –569
12 928 19.39655172 –178
13 1005 19.40298507 154
14 1082 19.40850277 438
15 1160 19.39655172 –178
16 1237 19.4017785
92
4.
Enumeration for R & N for f
M
= 19,440,000 Hz is shown in the table below:
R (try)
Nearest N
Required
VCXO(MHz)
VCXO tuning
(ppm)
1 77 19.48051948
2084
2 154 19.48051948
2084
3 231 19.48051948
2084
4 309 19.41747573
–1159
5 386 19.43005181
–512
6 463 19.43844492 –80
5.
The first table shows that R=16 and N=1237 allows us to generate 750 MHz
with the VCXO running 92 ppm above its nominal value.
