Circuit Description
80
CG635 Synthesized Clock Generator
SCK:
Serial clock output for synchronous data transfer to octal DAC and dual-modulus
synthesizer.
DAC/–PLL:
Controls the operation of the 20 MHz timebase. A high level allows the
frequency to be controlled by the CAL_10MHZ DAC output. A low level will cause the
20 MHz timebase to be phase locked to either an external 10 MHz input or to an
installed optional reference (rubidium or OCXO.)
–EXT/OPT:
Controls which high-precision source (either the external 10 MHz or an
internal OCXO or rubidium) is used as a frequency reference for the synthesizer. The bit
–EXT/OPT is set low to select the external 10 MHz reference or set high to select the
optional OCXO or rubidium.
EN_PRBS:
This bit is used to enable the optional PRBS generator. When low, the
PRBS shift register is loaded with all “ones”. When set high, the PRBS generates a
random binary sequence with a run-length of 127 bits.
Microcontroller Bi-directional Port
PORT_B:
Port B is used as a bidirectional port for reading and writing data to the GPIB
and DDS. Level translation and direction control between the microcontroller and the
DDS is provided by U503. Data flow is controlled by the following: a data direction
register in the microcontroller, –CE_GPIB (U501), –WR_GPIB (U501), DBIN_GPIB
(U501), –WR_DDS (U502), –RD_DDS (U502) and –CS_DDS (U500).
Analog Control Voltages
An octal 12-bit DAC (U504) provides analog voltages for system control. The DAC
outputs have 1 mV resolution between 0 V and 4.095 VDC. The functions of the eight
control voltages are detailed here:
CAL_OPT:
Used calibrate the frequency of an optional timebase (either rubidium or an
OCXO.) Nominal: +2.048 VDC. Scaled to 0 V to +5 V (for ± 0.02 Hz on PRS10) and 0
V to +10 V (for ±2.5 Hz on SC10-24-1-J-J-J-J)
CAL_20MHZ:
Used calibrate the frequency of the standard 20 MHz timebase (which is
divided by two to provide the rear-panel 10 MHz timebase output.) This voltage controls
the frequency of the timebase when no external reference is applied and no optional
timebase is installed. Full-scale range is about ±20 ppm. Nominal: +2.048 VDC.
CAL_TMOD:
Used to calibrate the sensitivity of the rear panel time modulation input
to 1 ns/V. Nominal: +2.048 VDC. Full scale range is approximately ±20 %.
CAL_SYM:
Used to calibrate the symmetry of the top octave output clock as indicated
when the difference bCLK_TST and –CLK_TST is zero. Increasing
CAL_SYM will deCLK_TST and increase –CLK_TST. The required value
may be a function of frequency.
Q_AMPL:
Controls the amplitude of the front panel Q & -Q outputs. The output
amplitude, Q
AMPL
, is given by: Q
AMPL
§
0.276 × Q_AMPL.
