Circuit Description
69
CG635 Synthesized Clock Generator
change (0.26 s). Note that at the top of this frequency band (at 2 MHz) the required
ǻ
f
for a 360° phase shift will be about 2 ppm.
(2) The accumulated phase error due to the rounding error in the computation of the
integer
ǻ
FTW at 2 GHz is equal to ½ LSB (max) × the number of DDS cycles during
the phase slew. In the top octave, where D=1, the
ǻ
t
pwm
will be 256 µs; hence, there are
100 MHz × 256 µs or 25,600 DDS cycles which can lead to a worst case phase error of
12,800 LSBs. This leads to a DDS output timing error of 12,800/2
48
periods or
16.4 nanodegrees at 2 GHz, which is very small compared to the 1° display resolution.
This method of phase slewing is quite satisfactory for high output frequencies, but can
take too long to execute at low frequencies. For example, a 360° phase shift at 1 Hz
would require 200,000 s (more than two days!) to perform if the frequency offset is
limited to 5 ppm. To overcome this restriction, output frequencies below 1 MHz are
sourced by a CMOS divider whose output can be quickly phase shifted by the CPU.
Phase shifts on outputs below 1 MHz can consist of two components: a small phase slew
component (which, as detailed above, is always used from high frequency phase
adjustments) and large phase jumps programmed into the CMOS divider.
Detailed Circuit Description
Note on reference designators:
The hundreds digit of the reference designator indicates
the schematic sheet number. For example, R200 is a resistor on Sheet 2 and U500 is an
integrated circuit on Sheet 5.
Note on PECL logic:
Most of the ECL logic used in this instrument is 100k series
operated from a +3.3 VDC power supply. The “high” level is +2.28 VDC and the “low”
level is +1.48 VDC, both of which follow the +3.3 VDC supply. An ECL output is
customarily terminated with a 50
ȍ
resistor to a potential which is 2.0 V below the V
cc
power (i.e., a 50
ȍ
resistor to +1.3 VDC.) Terminating both the Q & Q
¯ outputs on each
device will reduce system noise and allows termination to a node connected to ground
through the paralleled combination of a 50
ȍ
resistor and a 0.1 µF capacitor.
Timebase
Main Board, Schematic sheet “CG_MB1D”
The frequency reference for the CG635 Synthesized Clock Generator is a 20 MHz
Colpitts oscillator. The oscillator’s resonator (Y100) is a 3
rd
overtone AT-cut crystal
designed to operate at 20 MHz with a 20 pF load. The load capacitance is the series
combination of D100 (a dual varactor), C121 and C122 in parallel with L103. (The
oscillator will not operate at the fundamental mode of the resonator as the parallel
combination of C122 and L103 is inductive below 10.7 MHz.) Y100’s load capacitance
at 20 MHz is about 20 pF when the there is a reverse bias of 7 VDC across the dual
varactor. The bias to the varactor is provided by either a calibration voltage from a 12-bit
DAC or by a phase-lock loop (PLL) circuit if an external 10 MHz reference is applied or
if an optional 10 MHz reference is installed.
The 20 MHz sine output from the oscillator is converted to TTL logic levels by U112, an
AD8561 comparator. The 20 MHz square wave is used as the frequency reference for
