Stanford Research Systems CG635, User Manual

Page: 102 / 127

Circuit Description 88
CG635 Synthesized Clock Generator
SRS Model Logic output level
CG640 CMOS (+5.0 V
cc
)
CG641 CMOS (+3.3 V
cc
)
CG642 CMOS (+2.5 V
cc
)
CG643 PECL (+5.0 V
cc
, V
ee
=0)
CG644 PECL (+3.3 V
cc
, V
ee
=0)
CG645 PECL (+2.5 V
cc
, V
ee
=0)
CG646 RF (+7 dBm, ±0.5 V
dc
)
CG647 CML/NIM (0 V / -0.8 V)
CG648 ECL (V
ee
<0
,
V
cc
=0 )
CG649 LVDS
The CG640 +5 V CMOS receiver uses the RS-485 clock; all of the other receivers use
the LVDS clock. The maximum length of Category-6 cable that may be used with a
receiver will depend on the clock frequency and the type of Category-6 cable that is
used.
CG640 line receiver
Schematic sheet “CG_LR1B”
The CG640 line receiver converts the RS-485 differential clocks to complem5 V
CMOS outputs on SMA connectors.
The RS-485 level clock is received on the 7-8 pair of the RJ-45 connector (J400). The
differential signal is attenuated and terminated with 100
ȍ
by R101-R104. Undesired
common mode signals are terminated by R105 and C100. The unused LVDS level
clocks are terminated by R100. The RS-485 clock is converted to 3.3 V CMOS levels by
U101, a dual LVDS to CMOS line receiver. One of the translators in U101 is connected
in a non-inverting configuration while the other is connected in an
inverting configuration.
The complementary outputs of U400 drive the inputs of the hex buffers, U102 and U103
(CDC329). The six outputs from the two buffers are wired together to drive the SMA
output via a 50
ȍ
source impedance (R117-R122 or R123-R128). The 10.0
ȍ
resistors
(R107, R108, R112 & R113) in series with the Vcc bypass capacitors (C105-C108)
reduce output overshoot.
The outputs are intended to drive any length of un-terminated 50
ȍ
cable. The reflection
from the unterminated end is reverse terminated by the output’s 50
ȍ
impedance. The
resistors in the ground leads of U102 & U103 allow the source impedance for logic “0”
outputs to be matched to the source impedance of logic “1” outputs, allowing for a high
return loss for both levels.Terminating the outputs will not damage the module, but
doing so will reduce the amplitude of the outputs by a factor of 2×.
CG641 and CG642 line receivers
Schematic sheet “CG_LR2B”