Circuit Description
74
CG635 Synthesized Clock Generator
the time modulation input is 1 k
ȍ
for frequencies below 100 kHz, 50
ȍ
for frequencies
above 1 MHz, and is bandwidth limited to 200 kHz.
RF Synthesizer
Main Board, Schematic sheet “CG_MB3D”
The RF synthesizer consists of a VCO (U310), a fast PECL comparator (U304B), a
dual-modulus synthesizer (U307), and a charge-pump loop filter (U309 and various R’s
and C’s). The VCO can be tuned over more than an octave (960-2050 MHz). The
dual-modulus synthesizer has a very low noise floor (typically –159 dBc/Hz at a
comparison frequency of 1 MHz). The low-noise loop filter has an adjustable
proportional gain to minimize timing jitter as synthesizer parameters are changed.
Several measures are used to reduce the disturbance of the RF PLL by external sources
of noise and interference: (1) the VCO is powered by a low noise op-amp whose output
is 2.5 × the (filtered) 4.096 V reference, (2) SPI clock and data to the RF PLL (U307)
are gated “off” by U306 unless U307 is the intended target of the data transfer, (3) a
low-dropout linear regulator is used to power the dual-modulus synthesizer, and (4) the
charge pump is powered by the +4.096 V reference.
Low clock jitter (which is close to, but not exactly the same as low phase noise) is an
important design goal for the RF synthesizer. The dual-modulus synthesizer is a PLL
that phase locks the VCO frequency (divided by an integer N) to the reference frequency
(divided by an integer R). The VCO output frequency, f
vco
, is therefore set by the choice
of reference frequency, f
ref
, and the R and N divisors: f
vco
= f
ref
× N / R. The phase noise
of the VCO output cannot be better than the “multiplied up” (i.e., degraded by 6
dB/octave or 20 dB/decade) phase noise floor of the synthesizer at the comparison
frequency. For example, with a reference frequency of 19 MHz (as we have here) and an
R divider of 19 (which is close to the worst case, as we shall see), the comparison
frequency is 1 MHz, for which the synthesizer noise floor is typically –159 dBc/Hz. If
we are generating an output frequency near 1 GHz, which is three decades above the 1
MHz comparison frequency, the best phase noise we can expect from the VCO is
–159 + 3 × 20 = –99 dBc/Hz. So a key goal here is to operate the dual-modulus
synthesizer with small R divisors so as to keep the comparison frequency high to keep
the phase noise low.
We also need to be able to generate all frequencies between 960 MHz and 2050 MHz
with 16 digits of resolution. Large values of R and N would be required to achieve this
high resolution if the reference frequency was not tunable. However, using just two
reference frequencies (either 19.40 MHz or 19.44 MHz) that are tunable over a range of
±100 ppm we have the following remarkable results: (1) any frequency in the range of
960 MHz to 2050 MHz may be generated, (2) the average R divisor will be 8, (3) the
largest R divisor will be 25, and (4) the prime factors of 19.44 MHz (2
7
× 3
5
× 5
4
) are
such that many canonical frequencies can be generated with an R divisor of 1.
The output of the RF synthesizer is a complementary pair of +3.3 V PECL levels
(+RF_VCO and –RF_VCO) from U304B. These outputs have the following
characteristics: (1) Vhigh = +2.34 V, (2) Vlow = +1.55 V, (3) t
rise
= 175 ps, (4) t
fall
= 140
ps, (5) t
jitter
< 1 ps
rms
, (6) f
min
= 960 MHz, and (7) f
max
= 2050 MHz.
