Circuit Description
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CG635 Synthesized Clock Generator
Circuit Description
Overview
The CG635 Synthesized Clock Generator was designed with several goals in mind:
1.
Generation of square wave clocks from 1 µHz to 2050 MHz
2.
Very high frequency resolution for long-term phase stability
3.
Very low phase noise
4.
Low cost
The design benefits from several frequency synthesis techniques while avoiding the
pitfalls of those same techniques. For example, the design uses direct digital synthesis
(DDS) for unlimited frequency resolution while avoiding the high spurs associated with
DDS. The design also employs dual-modulus synthesis without suffering from the high
phase noise that often accompanies high resolution (i.e., close channel spacing) designs.
The CG635 was primarily designed to provide convenient clock sources for the testing
and operation of digital circuits and systems. Clock frequencies of up to 2.05 GHz may
be synthesized. However, the high accuracy, high resolution, and low phase noise of the
synthesized clock source will recommend its use in more esoteric tasks such as signal
heterodyning, bit error rate and network synchronization testing.
Accuracy
The frequency accuracy depends on the accuracy of the internal timebase. The standard
timebase is a 20 MHz crystal oscillator which provides an aging of <5 ppm per year. The
20 MHz timebase may be phase locked to an optional internal timebase or to an external
10 MHz source. Option 2, an ovenized crystal oscillator, provides an aging of <0.2 ppm
per year, while Option 3, a rubidium frequency standard, provides an aging of <0.0005
ppm per year.
Resolution
The frequency resolution of the CG635 is determined by the frequency resolution of the
DDS frequency synthesizer used in the system. The CG635 uses a 48-bit DDS; however
the frequency resolution is extended to 64 bits by frequency-shift keying (FSK) the least
significant bit (LSB) of the DDS with a duty factor with 16 bits of resolution. With this,
the fractional frequency resolution is about 1 : 3.58×10
18
providing an edge drift rate of
about 4.4 ps/year relative to a source with infinite resolution.
Phase Noise
Phase noise pitfalls are carefully avoided. The phase noise is essentially the multiplied
up (or divided down) phase noise of a fundamental mode, AT-cut crystal oscillator.
