Introduction 1
CG635 Synthesized Clock Generator
Introduction
Feature Overview
The CG635 Synthesized Clock Generator provides precise, low-jitter digital clock signals
for applications ranging from the development of digital circuits to the testing of
communications networks.
The CG635 generates single ended and differential clocks from 1 µHz to 2.05 GHz with
sub-picosecond jitter. Clock frequencies may be set with up to 1 pHz resolution and
16 significant digits. Front-panel outputs have continuously adjustable offsets and
amplitudes, and may be set to standard logic levels including CMOS, PECL, ECL, and
LVDS. A rear-panel output delivers clocks at RS-485 and LVDS over twisted pairs.
Several instrument features support more complex tasks. The phase of the outputs may be
adjusted with nanodegree resolution at 2 Hz, and one-degree resolution at 2 GHz. The
timing of clock edges may be modulated over ±5 ns by an external analog signal. An
optional pseudo-random binary sequence (PRBS) generator (Opt. 01) provides clock and
data outputs at LVDS levels for eye-pattern testing of serial data channels. Edge
transition times are typically 80 ps.
The standard crystal oscillator timebase of the CG635 provides sufficient accuracy for
many applications. An optional ovenized crystal oscillator (Opt. 02), or rubidium
frequency standard (Opt. 03), may be added to improve frequency stability and reduce
aging. The CG635 may also be locked to an external 10 MHz timebase.
The CG635 delivers a low spurious output signal—better than most commercial
synthesizers. Phase noise for a 622.08 MHz carrier at 100 Hz offset is less than
–80 dBc/Hz, and the spurious response is better than –70 dBc.
All instrument functions may be controlled from the front panel or via the GPIB (IEEE-
488.2) or RS-232 interfaces. Up to ten complete instrument configurations can be stored
in non-volatile memory and recalled at any time. A universal input AC power supply
allows world-wide operation.
Several clock receiver modules are available which may be connected to the rear-panel
RS-485/LVDS output via Category-6 cable. These accessories provide complementary
high-speed transitions at standard logic levels on SMA connectors, and may be located at
a substantial distance from the instrument. CMOS (+5 V, +3.3 V, and +2.5 V), PECL
(+5 V, +3.3 V and +2.5 V), RF (+7 dBm), CML/NIM, ECL, and LVDS outputs are all
available.
