Performance Evaluation
56
CG635 Synthesized Clock Generator
1.
With the power off hold down the ‘CLR’ button in the DISPLAY section and
turn the power on. This resets the SR620 to default settings.
2.
Press SOURCE button two times to switch the start pulse to REF.
3.
Press the SAMPLE SIZE
Ÿ
button six times to set the sample size to 1000.
4.
Press DISPLAY
ź
button five times to set the display to TRIG.
5.
Adjust the channel B trigger knob until the trigger level displayed for channel B
reads 0.00.
6.
Press the DISPLAY
Ÿ
button five times to set the display back to MEAN.
7.
Press the channel B ‘AC/DC’ button once to switch to AC coupling
8.
Press the channel B ‘INPUT’ button once to switch to 50
termination.
9.
Press ‘SEL’ in the CONFIG section until “SCN” is flashing
10. Press ‘SET’ in the CONFIG section until “DA Src chrt chrt” is displayed
11. Press SAMPLE SIZE
ź
once to change the display to “DA Src dac chrt”. This
configures the D/A output 1 to be sourced by the dac.
12. Press ‘SET’ in the CONFIG section once to display “DA 0.000 ---.---”
13. Press SAMPLE SIZE
ź
and
Ÿ
to adjust the DAC voltage to –5.00 V.
14. Press DISPLAY
Ÿ
to view the mean time interval.
15. Press ‘SET’ in the DISPLAY section to start showing relative measurements.
16. Press ‘SET’ in the CONFIG section until the display shows “DA –5.000 ---.---”
17. Press SAMPLE SIZE
ź
and
Ÿ
to adjust the DAC voltage to +5.00 V.
18. Press DISPLAY
Ÿ
to view the mean time interval.
19. Record the absolute value of the time interval as T
mod
T
mod
should meet the specifications given in Table 28.
Table 28: Time Modulation Specification
Voltage Swing
Min Mod. (ns)
Measured Mod. (ns)
Max Mod. (ns)
10 V
9.5
10.5
Phase Noise Tests
When making phase noise measurements, it is critical that the reference clock have
superior stability to that of the device under test. Use the setup shown in Figure 10 to
measure phase noise and jitter. Note that since the CG635 is locked to the FS725, this
setup will test the noise of the synthesizer alone, independent of the internal timebase.
Figure 10: Setup for phase noise and jitter tests.
Q
Q
CMOS
CG635
HP 89440A
RF IN
10 MHz IN
50
Ω
terminator
10 MHz IN
FS725
Rb Frequency Standard
