Circuit Description
75
CG635 Synthesized Clock Generator
ECL Dividers and Clock Multiplexer
Main Board, Schematic sheet “CG_MB4D”
The differential PECL clock from the RF synthesizer (+RF_VCO and –RF_VCO) is the
“top octave” clock that may be set from 960 MHz to 2050 MHz with 16 digits of
resolution. This clock is also used to clock ECL divider circuits that can divide the clock
by 2, 4, 8, 16, 32 … 1024. The output from the ECL divider may also be further divided
by U408, a programmable divider that has programmable phase jumps. An ECL 1:4
multiplexer (U404) is used to select one of four sources for output from the CG635: (1)
the undivided “top octave” clock, (2) the “top octave” clock divided by 2 by U400, (3)
the top octave clock divided by 4 × (256-ECL_DIV) where ECL_DIV is the 8-bit
“LOAD” value to the programmable counter, U401, or (4) the top octave clock divided
by 64 and further divided by a factor between 2
n
where 5
n
30 by U408. When the
“top octave” is selected, U411 disables the ECL dividers to reduce sub-harmonic
distortion. All clocks, both the inputs to and the outputs from the multiplexer U404, are
differ3.3 V PECL levels.
The ECL programmable divider was designed to operate to >1 GHz. The –TC output
from U401 goes low on the terminal count (i.e. when the counter reaches 255) and will
load the ECL_DIV value synchronously with the next clock. The –TC output is
pipelined (to meet propagation delay constraints) and inverted by U402, a D-type
flip-flop. The output of U402 is applied to the J&K inputs of the J/K flip-flop, U403.
The J/K flip-flop will toggle states with a clock if the J&K inputs are both high, and will
not change if the J&K inputs are both low. Therefore, the output of the J/K flip-flop is at
a rate equal to the top octave clock divided by 4 × (256-ECL_DIV) = 4, 8, 12, 16,
..1024.
The ECL divider can be used to generate clock outputs as low as 960 MHz/1024 or
937.5 kHz. Output frequencies below 937.5 kHz are generated by the CMOS
programmable divider (U408) which is clocked by the RF/64 via the TTL
comparator U407.
For frequencies above 1 MHz, phase adjustments to the output are accomplished by
running the DDS synthesizer off-frequency by a small amount (less than 5 ppm, as
limited by the headroom available in the VCXO tuning characteristic) for an accurately
controlled interval of time. The maximum phase step is limited to ±360°. At 1 MHz, the
clock edges will have to move by 1 µs for a 360° step. Running off-frequency by 5 ppm
for 200 ms will accomplish this phase step. At 1 GHz, a 360° step can be accomplished
with a 0.05 ppm frequency offset for an interval of 20 ms. And so phase adjustments can
be done quickly at frequencies above 1 MHz, even with a limited frequency offset.
However at an output frequency of 1 Hz, a 360° step would require running off
frequency by 5 ppm for 200,000 s (more than two days) which is clearly not acceptable.
An alternate approach to phase stepping is used for output frequencies below 1 MHz to
overcome this limitation. The programmable divider in U408 may be jumped ahead (or
backward) by an integer number of clock cycles allowing large instantaneous phase
jumps. High resolution phase steps at low output frequencies are accomplished by
combining both methods (phase step in the CMOS divider and phase slew by running
the DDS off-frequency for an accurately determined interval of time).
