Stanford Research Systems CG635 User Manual Download Page 5

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Contents

iii

CG635 Synthesized Clock Generator

Phase Noise Tests

Jitter Tests

Timebase Calibration

Timebase Calibration Test

Calibration 60

Circuit Description

Overview 61

Accuracy 61
Resolution 61
Phase Noise

Circuit Block Diagram

Timebase 62
Reference Synthesizer

Reference Synthesizer Clean-up

Time Modulation

RF Synthesizer

Programmable Dividers and Clock Fan-out

Determining Register Values

Phase adjustment

Detailed Circuit Description

Timebase 69
DDS and the 19.40/19.44 MHz Reference

Time Modulation

RF Synthesizer

ECL Dividers and Clock Multiplexer

Microcontroller 76
Rear-Panel RJ-45 Outputs

RS-232 and GPIB Interfaces

Power Supply Interface

Front-Panel Output Drivers

Front-Panel Q and Q

¯ Drivers

Front-Panel CMOS Driver

Front-Panel Display and Keypad

Power Supply

Timebase Options

Optional PRBS Generator

Line Receiver Accessories

Summary of Contents for CG635

Page 1: ...Revision 1 3 08 2010 User Manual CG635 2 05 GHz Synthesized Clock Generator www lambdaphoto co uk Distribution in the UK Ireland...

Page 2: ...t Service For warranty service or repair this product must be returned to a Stanford Research Systems authorized service facility Contact Stanford Research Systems or an authorized representative befo...

Page 3: ...dicators 7 Rear Panel Overview 8 AC Power 8 GPIB 8 RS 232 9 Chassis Ground 9 Timebase 9 Tmod Input 9 Clock Output 10 PRBS and Clock Option 11 Operation 13 Front Panel User Interface 13 Power On 13 Dis...

Page 4: ...s 31 Status Reporting Commands 31 Instrument Control Commands 32 Interface Commands 36 Status Reporting Commands 38 Status Byte Definitions 40 Serial Poll Status Byte 40 Standard Event Status Register...

Page 5: ...ammable Dividers and Clock Fan out 64 Determining Register Values 64 Phase adjustment 67 Detailed Circuit Description 69 Timebase 69 DDS and the 19 40 19 44 MHz Reference 71 Time Modulation 73 RF Synt...

Page 6: ...r Parts List 93 Motherboard Assembly 93 Output Driver Assembly 102 Power Supply Assembly 106 Chassis and Front Panel Assembly 107 Option 1 Assembly 109 Option 2 Assembly 111 Option 3 Assembly 111 Sche...

Page 7: ...r source and protective ground The exposed metal parts of the box are connected to the power ground to protect against electrical shock Always use an outlet which has a properly connected protective g...

Page 8: ...zed Clock Generator Symbols you may Find on SRS Products Symbol Description Alternating current Caution risk of electric shock Frame or chassis terminal Caution refer to accompanying documents Earth g...

Page 9: ...03 Rb 0 0005 ppm year External Input 10 MHz 10 ppm sine 0 5 Vpp 1 k impedance Output 10 MHz 1 41 Vpp sine 7 dBm into 50 Noise Spurs Phase noise at 622 08 MHz 100 Hz offset 90 dBc Hz 1 kHz offset 100 d...

Page 10: ...LOW 1 00 V Amplitude range 500 mV VAMPL 6 00 V VAMPL VHIGH VLOW Level resolution 10 mV Level error 2 of VAMPL 20 mV Transition time 1 0 ns 10 to 90 with 12pF load at far end of 50 cable Symmetry 500 p...

Page 11: ...0 Load impedance 50 to ground on all outputs Accessory Power on rear panel RJ 45 connector 5 VDC Pin 3 5 VDC Pin 5 Ground return Pin 4 and pin 6 Short circuit protection Current limited to 375 mA Pola...

Page 12: ...gh Z 800 ps 250 MHz CG644 3 3 V PECL 50 50 100 ps 2 05 GHz CG645 2 5 V PECL 50 50 100 ps 2 05 GHz CG646 7 dBm RF 50 50 100 ps 2 05 GHz CG647 CML NIM 50 50 100 ps 2 05 GHz CG648 NEG ECL 50 50 100 ps 2...

Page 13: ...mpedance input to see that the output is indeed a 3 3 V square wave with a frequency of 10 MHz 5 Adjust the frequency to 5 MHz by pressing the following keys sequentially 5 MHz The display should chan...

Page 14: ...n the ENTRY section of the front panel 1 kHz The display should now show 1 000000 kHz 13 Switch back to the frequency display be pressing the STEP SIZE key again The STEP LED should turn off and the d...

Page 15: ...erial data channels Edge transition times are typically 80 ps The standard crystal oscillator timebase of the CG635 provides sufficient accuracy for many applications An optional ovenized crystal osci...

Page 16: ...Keys on the front panel are divided into four sections to indicate their overall functionality OUTPUT LEVELS DISPLAY ENTRY and MODIFY Keys in the OUTPUT LEVELS section modify the amplitude and offset...

Page 17: ...3 20 PECL3 3V ECL run on 3 3 VDC supply 2 30 1 50 LVDS Low voltage differential signaling 1 43 1 07 7 dBm 1 Vpp with 0 0 VDC offset 0 50 0 50 ECL ECL run on negative supply 1 00 1 80 Table 2 CMOS Sta...

Page 18: ...appropriate units key to complete the entry For example if the frequency is currently being displayed pressing the keys 1 MHz sequentially will change the frequency to 1 MHz Similarly if the CMOS HIG...

Page 19: ...he Operation chapter page 22 The secondary functions can only be accessed when SHIFT mode is active which is indicated by the SHIFT LED being turned on The SHIFT mode can be toggled on and off by pres...

Page 20: ...you can increment and decrement the current step size by exact factors of ten by pressing the MODIFY and keys respectively For example if the currently displayed frequency step size is 1 000 Hz then...

Page 21: ...ms to stabilize A backward phase step of 360 degrees at 1 Hz can take as long as 1 5 s to complete The UNLK LED may also indicate that the internal clock has not locked to the external reference INTER...

Page 22: ...ltage requirements are 90 to 132 VAC or 175 to 264 VAC 47 to 63 Hz 80 VA total Connect the CG635 to a properly grounded outlet Consult an electrician if necessary GPIB The CG635 comes standard with a...

Page 23: ...er Chassis Ground Use this grounding lug to connect the CG635 chassis directly to facility ground Timebase 10 MHz IN The CG635 provides a 10 MHz BNC input for synchronizing its internal clock to an ex...

Page 24: ...th reduced amplitude Table 5 Optional Receiver Modules Model Description Termination Impedance Transition Time max Fmax 2 CG640 CMOS 5 Vcc High Z 2 0 ns 105 MHz 1 CG641 CMOS 3 3 Vcc High Z 800 ps 250...

Page 25: ...passes through the data transmission system An open eye pattern is necessary for reliable data transmission The eye pattern closes from the left and right with jitter and from the top and bottom with...

Page 26: ......

Page 27: ...ing out however the CG635 will not automatically save instrument settings that change due to commands executed over the remote interface The remote commands SAV and RCL can be used to explicitly save...

Page 28: ...ly difference is that the parameter step size must be displayed first before entering a new value If the user enters extra digits beyond the allowed resolution of a parameter the extra digits will be...

Page 29: ...ations 0 to 9 To save the current settings to location 5 for example press the keys STO 5 Hz sequentially To recall instrument settings from location 5 press the keys RCL 5 Hz sequentially The user ma...

Page 30: ...age differential signaling 1 43 1 07 7 dBm 1 Vpp with 0 0 VDC offset 0 50 0 50 ECL ECL run on negative supply 1 00 1 80 VHIGH and VLOW indicate the voltage driven by the Q and Q outputs for the high a...

Page 31: ...VHIGH VLOW would be 0 20 V VLOW will be set 0 20 V below VHIGH or VHIGH will be set 0 20 V above VLOW For example if the outputs are currently at LVDS levels setting VHIGH to 5 5 V will cause the CG6...

Page 32: ...n display by pressing CMOS HIGH and CMOS LOW keys in the DISPLAY section of the front panel The CMOS high and low voltages may be set to arbitrary values or stepped up and down by configurable step si...

Page 33: ...4567890 123456 Hz the CG635 s main display for frequency will be 1234567890 123 Hz If the user then presses and holds the FREQ key down the display will show 0 123456 Hz after a brief delay Similarly...

Page 34: ...ithin the same octave If an octave switch is required however and the frequency is in one of the first eleven bands the CG635 will disable the output forcing it low before changing the divider and sle...

Page 35: ...quency to 100 MHz the CG635 will change the phase and phase step sizes to 0 0 and 0 1 The user can define the current phase to be zero degrees by accessing the secondary function REL 0 The secondary f...

Page 36: ...front panel outputs with square waves at the selected frequency phase and amplitude settings The STOP function causes the CG635 to disable oscillation and force the outputs to a logic low state When...

Page 37: ...are currently unlocked Table 14 Synthesizer Lock Status Bit Name Meaning 0 RF_UNLOCK RF PLL is unlocked 1 19MHZ_UNLOCK 19 MHz PLL is unlocked 2 10MHZ_UNLOCK 10 MHz PLL is unlocked 3 RB_UNLOCK Optiona...

Page 38: ...off state is saved when instrument settings are saved If PRBS is installed the current status on off disabled of the PRBS can viewed via the STATUS function A status of disabled indicates that the PRB...

Page 39: ...Hardware Flow Control DATA This function enables the user to see the most recent characters received by the CG635 over the remote interface The characters are shown in hexadecimal format with older ch...

Page 40: ...19 44 MHz tuning The crystal can t tune to 100 ppm The CG635 may not be able to lock at all frequencies 3 19 40 MHz tuning The crystal can t tune to 100 ppm The CG635 may not be able to lock at all f...

Page 41: ...stable Wait 10 minutes to give the rubidium time to warm up and stabilize No GPIB communication Check that GPIB communication is enabled Sequentially press SHIFT GPIB Hz Also check that the GPIB addr...

Page 42: ......

Page 43: ...mmunications port The port is located on the rear panel of the CG635 The RS 232 interface connector is a standard 9 pin type D female connector configured as a DCE transmit on pin 3 receive on pin 2 T...

Page 44: ...nd The command buffer is limited to 255 bytes with 25 byte buffers allocated to each of up to three parameters per command If the command buffer overflows both the input and output buffers will be flu...

Page 45: ...mmands IDN Page 36 Identification String OPC Page 36 Operation Complete RCL i Page 36 Recall Instrument Settings RST Page 36 Reset the Instrument SAV i Page 36 Save Instrument Settings TST Page 37 Sel...

Page 46: ...Frequency step 7 Phase step 8 Q Q high step 9 Q Q low step 10 CMOS high step 11 CMOS low step The query form returns 1 if the current display does not correspond to one of the standard displays This...

Page 47: ...in the stopped state to i If i is 0 the stop level is low If i is 1 the stop level is high If i is set to 2 the stop level is toggled STDC i Standard CMOS Set query the CMOS output to i The parameter...

Page 48: ...olts 3 Q Q low step size in volts 4 CMOS high step size in volts 5 CMOS low step size in volts Example STPS 1 2 0 CR Set the phase step size to 1 degree STPS 0 CR Query the frequency step size STPU i...

Page 49: ...35 Remote Programming 35 CG635 Synthesized Clock Generator The parameter i selects the item i Display Item 0 Frequency 1 Frequency Step The parameter j selects the units j Display 0 Hz 1 kHz 2 MHz 3 G...

Page 50: ...nd phase step size 3 Q Q high and low levels and step sizes 4 CMOS high and low levels and step sizes 5 Current display selection 6 PRBS on off state 7 Run stop state 8 Stop level The display will be...

Page 51: ...s the instrument self test and returns 0 if successful and 72 EXE_FAIL_SELF_TEST if unsuccessful If unsuccessful the error buffer will include device dependent errors related to the parts of the self...

Page 52: ...ents If the value of the flag is 0 then the Service Request Enable and Standard Event Status Enable Registers SRE ESE are stored in non volatile memory and retain their values through power cycle even...

Page 53: ...ister Query the instrument status register The value returned is a decimal value from 0 to 255 After executing a INSR query the register is cleared See the Status Byte Definitions section for a descri...

Page 54: ...enable registers or clearing the status registers does not clear the enable registers Bits in the enable registers must be set or cleared explicitly To set bits in the enable registers write an intege...

Page 55: ...232 character may have been received incorrectly due to noise on the line 3 OR Overrun error An RS 232 character was received before the CG635 had time to process the previous character 4 OVFL The in...

Page 56: ..._UNLOCK The RF PLL has come unlocked 1 19MHZ_UNLOCK The 19 MHz PLL has come unlocked 2 10MHZ_UNLOCK The 10 MHz PLL has come unlocked 3 RB_UNLOCK The optional rubidium oscillator has come unlocked 4 OU...

Page 57: ...was illegal 31 Phase Step Error The phase could not be set because it would have caused a phase step larger than 360 40 Voltage Error The voltage could not be set because it was out of range 51 Q Q L...

Page 58: ...110 Illegal Command The command syntax used was illegal A command is normally a sequence of four letters or a followed by three letters 111 Undefined Command The specified command does not exist 112...

Page 59: ...led 19 44 MHz Low Rail The 19 44 MHz crystal can not tune to low enough frequencies 154 Failed 19 44 MHz High Rail The 19 44 MHz crystal can not tune to high enough frequencies 155 Failed 19 40 MHz Lo...

Page 60: ...Q Q high output is out of specification 163 Failed Optional Timebase An installed optional timebase is not oscillating 164 Failed Clock Symmetry The clock output symmetry is out of specification Othe...

Page 61: ...ng the frequency generation at various points in the spectrum from DC to 2 05 GHz Lastly the timebase calibration tests evaluate the accuracy and stability of the installed timebase Equipment Required...

Page 62: ...be damaged 8 Option detection Optional oscillator is installed but not oscillating The CG635 will use its internal oscillator The CG635 self test is automatically executed at power on It may also be e...

Page 63: ...25 2 333 PECL 5V 3 158 3 950 3 242 4 050 To test the Q output configure the CG635 as in Figure 4 except swap the connections to Q and Q Repeat the steps above except record Vhigh in step 4 and record...

Page 64: ...urement setup Connect 20 dB attenuators to the inputs of the HP 54121A Use short equal length SMA cables with SMA to BNC adaptors to connect the CG635 to the HP 54121A Setup the CG635 as follows 1 Pre...

Page 65: ...Measure the rise time by adjusting the T Markers so that the Start Marker is located at the point where the waveform crosses V Marker 1 and the Stop Marker is located at the point where the waveform c...

Page 66: ...sses V Marker 2 Record the t of the markers as the rise time of the given waveform Add 2 5ns to the reference delay to center the falling edge transition in the display Measure the fall time by adjust...

Page 67: ...7 Press the DISPLAY button five times to set the display back to MEAN 8 Press the channel A AC DC button once to switch to AC coupling 9 Press the channel A INPUT button once to switch to 50 terminat...

Page 68: ...z The SR620 can measure frequencies below 1 0 GHz directly Use the setup shown in Figure 8 for frequencies from 100MHz to 1 0 GHz Configure the SR620 as described above Make sure that the channel A in...

Page 69: ...000 010 10 0 9 999 999 990 10 000 000 010 20 0 19 999 999 900 20 000 000 100 50 0 49 999 999 900 50 000 000 100 100 0 99 999 999 900 100 000 000 100 Time Modulation Test The time modulation test verif...

Page 70: ...12 Press SET in the CONFIG section once to display DA 0 000 13 Press SAMPLE SIZE and to adjust the DAC voltage to 5 00 V 14 Press DISPLAY to view the mean time interval 15 Press SET in the DISPLAY sec...

Page 71: ...On Num averages 100 Frequency Center 622 08 MHz Span 400 Hz Marker Enter marker position 100 Hz The settings marked with a will change at each test point as specified in Table 30 below Phase Noise Tes...

Page 72: ...e a reasonable approximation of the jitter HP 89440A Configuration First press the Preset key to force the unit to default settings Then enter the settings detailed in Table 31 Table 31 HP 89440A conf...

Page 73: ...se installed in the CG635 Use the setup shown in Figure 11 to test the accuracy of the timebase Figure 11 Setup for timebase calibration The accuracy and stability of the CG635 timebase depends on the...

Page 74: ...Timebase Calibration Test It is critical that the timebase be fully warmed up before measurements are taken Allow at least 1 hour of warm up for an OCXO or Rubidium timebase Allow at least 30 minutes...

Page 75: ...use in more esoteric tasks such as signal heterodyning bit error rate and network synchronization testing Accuracy The frequency accuracy depends on the accuracy of the internal timebase The standard...

Page 76: ...0 MHz timebase as a reference to generate a frequency near i e within 100 ppm either 19 400 000 Hz or 19 440 000 Hz The output of the DDS synthesizer is used as a frequency reference for the RF synthe...

Page 77: ...uency by a factor N 40 N 65591 with the restriction that N 46 47 or 55 more on this quirky numerology later and compares the divided frequencies with a phase frequency detector The phase comparison fr...

Page 78: ...24 000 000 2 4 240 000 000 512 000 000 3 8 120 000 000 256 000 000 4 16 60 000 000 128 000 000 5 32 30 000 000 64 000 000 6 64 15 000 000 32 000 000 7 128 7 500 000 16 000 000 8 256 3 750 000 8 000 00...

Page 79: ...N and FTW is 1 Use Table 34 to determine the output divider D If possible stay within the current band i e use the current value for D 2 Compute the required RF VCO frequency fVCO fO D 3 Find the lowe...

Page 80: ...19 35483871 2328 3 232 19 39655172 178 4 309 19 41747573 901 5 387 19 37984496 1039 6 464 19 39655172 178 7 541 19 40850277 438 8 619 19 38610662 716 9 696 19 39655172 178 10 773 19 40491591 253 11 85...

Page 81: ...ividers for the 1 090 000 frequencies spaced by 10 kHz 10 ppm were computed and statistics were complied The following results were obtained with available VCXO frequencies of 19 400 000 Hz and 19 440...

Page 82: ...lator This accumulating error degrades the accuracy with which we are setting the phase and so we must limit the number of times that the LSB error sums into the phase This restriction is accommodated...

Page 83: ...r example R200 is a resistor on Sheet 2 and U500 is an integrated circuit on Sheet 5 Note on PECL logic Most of the ECL logic used in this instrument is 100k series operated from a 3 3 VDC power suppl...

Page 84: ...tor U102 is used to convert the 10 MHz sine wave from an optional internal timebase either an SC10 ovenized oscillator or a PRS10 rubidium frequency standard into TTL logic levels The low pass filter...

Page 85: ...ternal 10 MHz reference the PLL integrator will be pre charged to the voltage for which the 20 MHz timebase was last calibrated Also the microcontroller can calibrate the 20 MHz timebase finding the v...

Page 86: ...FSK will cause a clock output to time shift by 7 ps year relative to an ideal source which is considered to be negligible The two VCXOs one at 19 40 MHz and the other at 19 44 MHz operate continuousl...

Page 87: ...ibrated to have a sensitivity of 1 ns V and a full scale range of 5 ns The input is DC coupled and so may be used as a DC phase adjustment of the clock outputs Broadband noise applied to this input wi...

Page 88: ...y fref and the R and N divisors fvco fref N R The phase noise of the VCO output cannot be better than the multiplied up i e degraded by 6 dB octave or 20 dB decade phase noise floor of the synthesizer...

Page 89: ...a clock if the J K inputs are both high and will not change if the J K inputs are both low Therefore the output of the J K flip flop is at a rate equal to the top octave clock divided by 4 256 ECL_DI...

Page 90: ...5D The microcontroller U500 is a MC68HC912D60A The important features used in this design include 1 16 bit device with hardware math operations 2 60k bytes of flash ROM for program instructions 3 2k b...

Page 91: ...the 19 4 MHz timebase to the DDS 19MHZ_LAG is a voltage proportional to the amount by which DDS lags the 19 4 MHz VCXO The front panel UNLOCK LED will be lit if 19MHZ_LEAD and 19MHZ_LAG are not betwee...

Page 92: ...The scaling network has a high impedance so as to source only 200 A from the 24 V standby power supply when the instrument is turned off RS 232 Interfaces RTS_RS232 Request to Send input to CPU from t...

Page 93: ...m either 5 V or 3 3 V as required by the target CS_GPIB_CTL Port strobe for GPIB interface latch CS_DDS_CTL Port strobe for DDS interface latch CS_DDS Port strobe for DDS bi directional read or write...

Page 94: ...wing a data direction register in the microcontroller CE_GPIB U501 WR_GPIB U501 DBIN_GPIB U501 WR_DDS U502 RD_DDS U502 and CS_DDS U500 Analog Control Voltages An octal 12 bit DAC U504 provides analog...

Page 95: ...nable U511 Programmable ECL divider load value U512 Band select output enable PRBS enable LVDS enable Microcontroller Display and Keypad Scanning Four of the octal latches U506 U509 are used to refres...

Page 96: ...ated with a 1 8th duty factor should the microcontroller stop operating The second half of U505 is used to generate a key click sound when the MSB of U508 is set high Rear Panel RJ 45 Outputs Main Boa...

Page 97: ...the power switch is on This power supply powers the optional timebase an OCXO or rubidium even while the instrument is off LED lamps on the main circuit board and in the modular power supply indicate...

Page 98: ...ck signal The MAX3737 U105 is a laser diode driver and it is used in this application to provide an extremely fast current switch The 3 3V part has a very limited output voltage compliance range and s...

Page 99: ...tion of R250 R252 in parallel with the series combination of R247 R249 The parallel combination of L200 and R253 match return pulses into the collector capacitance of Q204 and Q206 providing a high re...

Page 100: ...1 Timebase Options Schematic sheet CG_TB1B There are two timebase options an OCXO SRS p n SC 10 24 1 J J J J and a rubidium frequency standard SRS p n PRS10 The optional timebases are held by the same...

Page 101: ...rcle to minimize delays in the data path Data propagates clockwise around the circle The clock is arranged to propagate counterclockwise along a differential transmission line with a 20 impedance A co...

Page 102: ...level clocks are terminated by R100 The RS 485 clock is converted to 3 3 V CMOS levels by U101 a dual LVDS to CMOS line receiver One of the translators in U101 is connected in a non inverting configu...

Page 103: ...sheet CG_LR3B The CG643 CG645 line receivers convert differential LVDS clocks to complementary PECL outputs on SMA connectors These three line receivers use the same PCB and circuit design The voltag...

Page 104: ...transistor Q400 imitates a laser diode s photo monitor by providing small current that increases with the MAX3737 s bias current generator U404 provides a reset to U403 in the case that a fault shoul...

Page 105: ...ed RS 485 level clocks are terminated by R600 The LVDS clock input is AC coupled to an ECL line receiver U602 The clocks DC levels are summed with the AC levels by the slow differential amplifiers U60...

Page 106: ......

Page 107: ...MT1206 50V 5 NPO C 123 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 124 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 125 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 126 5 00372 552 56P Ca...

Page 108: ...amic 50V SMT 1206 10 X7R C 260 5 00387 552 1000P Capacitor Chip SMT1206 50V 5 NPO C 261 5 00371 552 47P Capacitor Chip SMT1206 50V 5 NPO C 262 5 00379 552 220P Capacitor Chip SMT1206 50V 5 NPO C 263 5...

Page 109: ...p Ceramic 50V SMT 1206 10 X7R C 407 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 408 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 409 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 410 5 002...

Page 110: ...1000P Capacitor Chip SMT1206 50V 5 NPO C 618 5 00318 569 2 2U T35 Cap Tantalum SMT all case sizes C 619 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 622 5 00299 568 1U Cap Ceramic 50V SMT 1206 10...

Page 111: ...Ferrite bead SMT L 606 6 00236 631 FR47 Ferrite bead SMT N 500 4 01716 463 270X4 Resistor network SMT Leadless N 501 4 01716 463 270X4 Resistor network SMT Leadless N 502 4 01716 463 270X4 Resistor ne...

Page 112: ...pm MELF Resistor R 130 4 01059 462 249 Thin Film 1 50 ppm MELF Resistor R 131 4 01059 462 249 Thin Film 1 50 ppm MELF Resistor R 132 4 01447 461 47 Thick Film 5 200 ppm Chip Resistor R 134 4 01447 461...

Page 113: ...ppm MELF Resistor R 305 4 01117 462 1 00K Thin Film 1 50 ppm MELF Resistor R 307 4 01309 462 100K Thin Film 1 50 ppm MELF Resistor R 308 4 00992 462 49 9 Thin Film 1 50 ppm MELF Resistor R 309 4 01021...

Page 114: ...pm Chip Resistor R 411 4 01447 461 47 Thick Film 5 200 ppm Chip Resistor R 412 4 01038 462 150 Thin Film 1 50 ppm MELF Resistor R 413 4 01038 462 150 Thin Film 1 50 ppm MELF Resistor R 414 4 01503 461...

Page 115: ...5 3 3 Integrated Circuit Surface Mount Pkg U 106 3 00978 360 74LVC74 Integrated Circuit Surface Mount Pkg U 107 3 01204 360 SN74LVC1G32DBVR Integrated Circuit Surface Mount Pkg U 108 3 00643 360 DG211...

Page 116: ...4 Integrated Circuit Surface Mount Pkg U 509 3 00751 360 74HC574 Integrated Circuit Surface Mount Pkg U 510 3 00751 360 74HC574 Integrated Circuit Surface Mount Pkg U 511 3 01206 360 74LVC574ADW Integ...

Page 117: ...50V 5 NPO C 203 5 00358 552 3 9P Capacitor Chip SMT1206 50V 5 NPO C 204 5 00611 578 4 7U 16V X5R SMT Ceramic Cap all sizes C 205 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 206 5 00299 568 1U Cap...

Page 118: ...2 462 49 9 Thin Film 1 50 ppm MELF Resistor R 116 4 01117 462 1 00K Thin Film 1 50 ppm MELF Resistor R 117 4 01117 462 1 00K Thin Film 1 50 ppm MELF Resistor R 118 4 01067 462 301 Thin Film 1 50 ppm M...

Page 119: ...Film 1 50 ppm MELF Resistor R 239 4 00971 462 30 1 Thin Film 1 50 ppm MELF Resistor R 240 4 01059 462 249 Thin Film 1 50 ppm MELF Resistor R 241 4 01213 462 10 0K Thin Film 1 50 ppm MELF Resistor R 2...

Page 120: ...4 7U Capacitor Tantalum 35V 20 Rad C 17 5 00143 536 1200P Capacitor Ceramic 1000 VDCW C 18 5 00516 526 330U HIGH RIPPL Capacitor Electrolytic 35V 20 Rad C 19 5 00102 517 4 7U Capacitor Tantalum 35V 20...

Page 121: ...ardware Z 0 0 00185 021 6 32X3 8PP Screw Panhead Phillips Z 0 0 00187 021 4 40X1 4PP Screw Panhead Phillips Z 0 0 00210 020 4 40X5 16PF Screw Flathead Phillips Z 0 0 00222 021 6 32X1 4PP Screw Panhead...

Page 122: ...D 38 3 00004 301 1N4148 Diode D 39 3 00004 301 1N4148 Diode D 40 3 00004 301 1N4148 Diode JP1 1 00661 130 5 PIN SI TIN Connector Male JP2 1 00661 130 5 PIN SI TIN Connector Male JP3 1 00661 130 5 PIN...

Page 123: ...9 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 6 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 7 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 8 5 00299 568 1U Cap Ceramic 50V SMT 1206 10 X7R C 9 5...

Page 124: ...5 200 ppm Chip Resistor R 25 4 01447 461 47 Thick Film 5 200 ppm Chip Resistor R 26 4 01447 461 47 Thick Film 5 200 ppm Chip Resistor R 27 4 01447 461 47 Thick Film 5 200 ppm Chip Resistor R 28 4 014...

Page 125: ...0 00048 011 6 32 KEP Nut Kep Z 0 0 00096 041 4 SPLIT Washer Split Z 0 0 00241 021 4 40X3 16PP Screw Panhead Phillips Z 0 0 01090 031 3403 Standoff Z 0 1 01057 130 26 48 1101 Connector Male Z 0 6 0005...

Page 126: ......

Page 127: ...ers CMOS CG_DR2F 11 Power supply inverter CG_PS1B 12 PRBS Generator Option 1 CG_PR1B 13 Timebase adapter Options 2 3 CG_TB1B 14 Line receiver accessory CG640 CG_LR1B 15 Line receiver accessory CG641 C...

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