Circuit Description
68
CG635 Synthesized Clock Generator
So, delaying the DDS edges by 401.877 ps will cause a 90º phase shift of a 622.08 MHz
output. In contrast, if the user requests a phase change of 360° for a 1 MHz output, the
DDS edges would have to be moved by 1 µs.
While the DDS has the capability to do phase-shift-keying, it cannot adjust the phase of
the output directly; instead, the edges of the DDS output will be moved by operating the
DDS at a nearby frequency for a short period of time.
If the frequency tuning word (FTW) of the DDS is changed from its value by
ǻ
FTW,
and the DDS is operated at this new frequency for a time
ǻ
t
pwm
, then the DDS edges will
advance in time by:
ǻ
T
DDS
= (
ǻ
FTW/ FTW)×
ǻ
t
pwm
There is an important restriction on the magnitude of
ǻ
FTW/FTW: the DDS frequency
change must not be so large as to cause the VCXO to come unlocked from the DDS. We
will restrict
ǻ
FTW/FTW to be less than ±10 ppm. This restriction requires a relatively
long
phase slew interval in order to achieve the desired time shift.
There is another restriction: we need to make sure that the quantization error on
ǻ
T
DDS
(due to the rounding in the calculation on the integer
ǻ
FTW) does not significantly
degrade the phase setting. Every cycle of the DDS (which occur at 100 MHz) may add
up to ½ LSB of error to the 48-bit phase accumulator. This accumulating error degrades
the accuracy with which we are setting the phase and so we must limit the number of
times that the ½ LSB error sums into the phase. This restriction is accommodated by
choosing a relatively
short
phase slew interval in order to limit the accumulated error.
Gratefully, there is an overlap between the
long
and the
short
restrictions on
ǻ
t
pwm
. The
ǻ
t
pwm
FSK pulse is generated by a single pulse from the microcontroller’s PWM. The
pulse generator uses a clock with a period of 25.6 µs (ECLK/128 or XTAL/256.) The
pulse generator will be programmed to use 10 × D cycles of this clock to generate a
ǻ
t
pwm
between 256 µs and 262,114 µs. (Recall D is the frequency synthesizer output
divider and D=1, 2, 4…1024.)
Given this, we can look at two limiting cases: (1) the frequency de-tuning required to
produce a phase step of 360° at 937.5 kHz (the largest phase step at the lowest frequency
which is adjusted in this manner) and (2) the accumulated phase error for a phase step at
2.05 GHz given a ½ LSB error in the calculation of
ǻ
FTW.
(1) The time delay required to phase shift 937.5 kHz by 360° is given by:
ǻ
T
DDS
= (1/937.5×10
3
)
§
1.06666 µs (one period for 360°)
At this frequency, the output divider D is 1024 and so
ǻ
t
pwm
will be 262,114 µs. In order
to slew by 1.06666 µs in an interval of 262,114 µs will require:
ǻ
FTW/FTW =
ǻ
T
DDS
/
ǻ
t
pwm
= 1.06666 µs / 262,114 µs = 4.069476 ppm
So we see that
ǻ
t
pwm
is long enough to avoid having the VCXO come unlocked
(
ǻ
f
§
4 ppm), but not so long as to cause the user to grow impatient with the phase
