Circuit Description
67
CG635 Synthesized Clock Generator
6.
The second table shows that R=6 and N=463 allows us to generate 750 MHz
with the VCXO running 80 ppm below its nominal value.
7.
The value from the second table is preferred, as the lower N value will provide a
lower phase noise, and so the 19,440,000 Hz VXCO will be selected. The phase
comparison frequency in the RF PLL will be about 3.23 MHz.
8.
For N=463, N = 8 × B + A, so the B counter will be loaded with 57 and the A
counter will be loaded with 7.
9.
Finally, compute the DDS frequency tuning word:
FTW = f
O
× D × R × 2
64
/ (f
R
× M × N)
= 750,000,000 × 2 × 6 × 2
64
/ (20,000,000 × 5 × 463)
§
3.58 × 10
18
The top 48-bits of the FTW are sent to the DDS synthesizer and the 16 LSBs are used to
control the FSK PWM. The FTW may only be correct to ½ LSB. This quantization error
leads to a frequency setting error of about ½ part in 3.58 × 10
18
, which would cause a
phase drift of about 4.4 ps/year relative to an ideal source.
Typical values for the R divider
A program was written to find R & N divider values for output frequencies in the top
band (960-2050 MHz). R & N dividers for the 1,090,000 frequencies spaced by 10 kHz
(10 ppm) were computed and statistics were complied. The following results were
obtained with available VCXO frequencies of 19,400,000 Hz and 19,440,000 Hz (with a
tuning range of ±100 ppm): R
min
= 1, R
mean
= 8.02 and R
max
= 26. About 99.9% of the
computed R dividers were
20. The maximum R value of 26 provides a phase
comparison frequency of 747 kHz, where the phase noise floor of the dual modulus
synthesizer is typically –159 dBc/Hz. If this comparison frequency is being used to
generate an output frequency 1,000 × higher (i.e. at 747 MHz), one would expect an
output phase noise of approximately –159+60 = –99 dBc/Hz.
Phase adjustment
The CG635 allows the phase of the output to be viewed and adjusted from the front
panel or via the computer interface. Since the output edges are phase locked to the
internal DDS edges, output edges will move by the same amount of
time
as the DDS
edges. Therefore, the instrument can adjust the phase of its output by adjusting the
timing of the DDS edges.
The user enters a phase change in
degrees
and the instrument computes a corresponding
time
change. For example, if the user requests a 90º phase change for an output at
622.08 MHz this corresponds to a time delay of:
ǻ
T = (1/622.08×10
6
) × (90º / 360º)
§
401.877 ps
