Circuit Description
87
CG635 Synthesized Clock Generator
pseudo-random bit sequence which repeats after 2
7
– 1 = 127 clock cycles. The data
stream satisfies many criteria to qualify as “random”, however it does repeat itself,
exactly, after 127 clock cycles. Another departure from randomness is that the longest
string of “1’s” is seven in a row while the longest string of “0’s” is six in a row.
The 7-bit PRBS generator consists of seven D-type flip-flops (U1-U7) and one
exclusive-or gate (U8). All clocks and data are passed differentially for lowest noise and
maximum speed. The exclusive-or of the 6
th
and 7
th
bits are feedback to the shift register
input. The 7
th
bit is used as the PRBS output (any bit would do) and it is buffered
by U10.
The critical timing path, which determines the highest clock frequency for which the
circuit will operate, is through the exclusive-or gate. The impact of the exclusive-or’s
propagation delay is reduced by phasing the clocks. Delaying the clock to U1 by 250 ps
effectively removes 250 ps of the exclusive-or’s 330 ps (worst case) propagation delay,
thereby allowing the circuit to operate above 2 GHz. The clock is advanced by 50 ps in
each successive stage so that the data meets the setup time for the un-delayed clock at
U6. The technique effectively spreads out the exclusive-or’s propagation delay over five
stages allowing the circuit to operate at a much higher frequency.
The layout of this circuit on the PCB is critical to its operation. The seven flip-flops are
arranged in a circle to minimize delays in the data path. Data propagates clockwise
around the circle. The clock is arranged to propagate counterclockwise along a
differential transmission line with a 20
ȍ
impedance.
A control bit from the microcontroller, EN_PRBS, is set high to enable the PRBS.
Setting EN_PRBS low will force the input to U1 to be a “1”. Seven additional clock
cycles are required for the rear-panel PRBS output to go to “1” after EN_PRBS is set
low. The PRBS output will stay high until 7 clock cycles after the EN_PRBS goes
high again.
Both the PRBS data and the clock are output as LVDS levels on rear panel SMA
connectors. The PRBS data is buffered by the U10 and converted to LVDS levels by
R48-R53. The clock is buffered by the U11 and converted to LVDS levels by R54-R59.
These resistor networks also reverse terminate the LVDS source with the 100
ȍ
characteristic impedance of the UTP cable.
Line Receiver Accessories
The rear-panel of the CG635 has an RJ-45 connector to provide clock signals at RS-485
and LVDS levels as well as ±5 VDC. A series of line receiver accessories are used to
receive the clock signals over an unshielded, four-pair, CAT-6 cable and convert the
clock to single-ended complementary logic outputs on SMA connectors. In addition to
being a useful accessory, these devices demonstrate the use of the RJ-45 outputs.
Ten different clock receivers are available as accessories to provide complementary
clock outputs on SMA connectors at standard logic levels. The SMA outputs are
intended to drive 50
ȍ
coax cables terminated with 50
ȍ
loads to ground (with the
exception of the CMOS and the +5 V PECL receivers, which are intended to drive
unterminated 50
ȍ
coax cables.) The following types are available:
