Circuit Description
84
CG635 Synthesized Clock Generator
Front-Panel Q and Q
¯ Drivers
Driver Board, Schematic sheet “CG_DR1F”
The Q and Q
¯ outputs are high speed (DC-2.05 GHz with transitions times of <100 ps),
low amplitude (0.2 V to 1.0 V), differential outputs designed to be terminated into 50
ȍ
loads. The outputs’ high level can be as high as +5 VDC or as low as –2 VDC to be
compatible with a variety of logic families (+5 V PECL, +3.3 V PECL, LVDS, RF,
ECL, RSECL, etc.) If either the Q or Q
¯ output is used, both outputs should be terminated
with 50
ȍ
to ground.
Each of the Q and Q
¯ outputs consist of two series 24.9
ȍ
resistors (to provide a source
impedance of 50
ȍ
) connected to a programmable voltage source (U100). The
programmable voltage source is set to twice the high level for the desired logic output.
This voltage source must always source current to operate properly. In the case of
negative output offsets it is necessary to load the voltage source, which is done by
U107B and Q101.
A fast, differential, current sink provided by U105 (MAX3737) alternates between the Q
and Q
¯ outputs under the control of the ±Q_DRV clock signals. An output is pulled low
when current is drawn from that output by U105. The current source is programmed by
the analog control voltage Q_AMPL. Increasing the current source increases the
amplitude of the output clock signal.
The MAX3737 (U105) is a laser diode driver, and it is used in this application to provide
an extremely fast current switch. The 3.3V part has a very limited output voltage
compliance range, and so it is operated from two power supplies which track the
outputs’ high level. The ±Q_DRV clock signals which switch the fast current sink are
AC coupled to U105 via C111 and C112, and the DC levels for these logic signals are
maintained by the (slow) differential amplifiers U104A and U104B.
The MAX3737 has other features which are not used here but which need to be
accommodated so as to avoid apparent “fault” conditions. The transistor Q100 imitates a
laser diode’s photo monitor by providing small current that increases with the
MAX3737’s bias current generator. U106 provides a reset to U105 in the case that a
fault should occur.
The Q and Q
¯ output levels may be sampled by the microcontroller via the ±Q_TST
outputs which are attenuated, offset and filtered versions of the Q and Q
¯ outputs. These
test points allow the microcontroller to verify operation, check for user termination, and
calibrate the output amplitudes and offsets of the Q and Q
¯ outputs.
Front-Panel CMOS Driver
Driver Board, Schematic sheet “CG_DR2F”
The front-panel CMOS driver is a high-level (up to 6 V), fast transition time (<1.0 ns),
cable driver with a 50
ȍ
source impedance. The baseline for the output, which is
normally at 0 VDC, may be offset by ±1.00 VDC. This output is normally not
terminated with 50
ȍ
. Doing so will not damage the output, and will improve the
