Circuit Description
63
CG635 Synthesized Clock Generator
Reference Synthesizer Clean-up
The frequency reference from the DDS is “cleaned-up” by one of two VCXOs. One of
the VCXOs (either the 19,400,000 Hz VCXO or the 19,440,000 Hz VCXO) is selected
(by a procedure to be detailed later) and loosely phase locked to the DDS output. The
natural frequency of this PLL is only a few Hertz, and so the VCXO will not pass spurs
more than a few Hertz away from the carrier. The VCXO can lock to input frequencies
with a capture range of at least ±100 ppm (±1944 Hz). The output of the VCXO provides
a spur-free reference frequency to the RF synthesizer which follows.
Time Modulation
The output from the selected VCXO is converted to a triangle ramp and applied to the
input of a high speed comparator. The external “time modulation” input is applied to the
other input of the comparator, allowing the external modulation source to linearly delay
or advance the transitions at the output of the comparator. Since the RF synthesizer
phase locks the RF VCO to the reference, the RF VCO timing will follow the
modulation applied to the reference (up to the bandwidth of the RF PLL.)
RF Synthesizer
A dual-modulus RF frequency synthesizer is used to phase lock a 960-2050 MHz VCO
to the cleaned-up DDS reference. The RF frequency synthesizer divides the DDS
reference by a factor “R” (1
R
16,383), divides the VCO frequency by a factor “N”
(40
N
65591 with the restriction that N
46, 47 or 55…more on this quirky
numerology later), and compares the divided frequencies with a phase/frequency
detector. (The phase comparison frequency will be the DDS frequency / R.) The output
of the phase/frequency detector operates a charge pump which in turn controls the
frequency of the VCO to achieve phase lock.
For a low phase noise output, it is important that the R & N divisors be as small as
possible; the instrument’s output phase noise can be no better than the dividers’ and
phase detector’s phase noise floor (typically –159 dBc/Hz at 1 MHz) multiplied up from
the phase comparison frequency to the output frequency. (The output phase noise will
suffer 20 dB phase noise degradation per decade of frequency between the phase
comparison frequency and the output frequency.)
The R & N dividers are determined by enumeration, starting with R=1 and determining
if there is an N value that will provide the desired output frequency from a reference of
19,400,000 Hz ± 100 ppm or 19,440,000 Hz ± 100 ppm. Computer enumeration shows
that the average R value is 8 and no R value larger than 26 is required to synthesize any
frequency. (The R values with two VCXOs are about four times lower than they would
be with just one VCXO. The R values would be smaller if the tuning range of the
VCXOs was larger.)
A low pass filter (with a bandwidth that is decreased as the R divider is increased) filters
the dual modulus synthesizer’s phase detector output. The output of the filter controls
the VCO which can operate over the range of 960-2050 MHz.
