Circuit Description
91
CG635 Synthesized Clock Generator
fault should occur. The magnitude of the current switched by U503 is controlled by
R510.
Both SMA outputs should be terminated with 50
ȍ
loads.
CG649 line receiver
Schematic sheet “CG_LR6B”
The CG649 line receiver reconstructs the LVDS differential clocks to provide
complementary LVDS outputs on SMA connectors.
The LVDS level clock is received on the 1-2 pair of the RJ-45 connector, J600. The
differential signal is (primarily) terminated by R602 and R603. Undesired common
mode signals are terminated by R604 and C601. The unused RS-485 level clocks are
terminated by R600.
The LVDS clock input is AC coupled to an ECL line receiver, U602. The clocks’ DC
levels are summed with the AC levels by the (slow) differential amplifiers U601A and
U601B. The open emitter outputs of U602 are biased on and terminated by N601 and
subsequently drive the inputs to U603. The PECL outputs of U603 are converted to
LVDS levels by the resistor network R609-R614, which also provides a 50
ȍ
source
impedance to drive the SMA outputs. Both U602 and U603 are powered by the low
dropout regulator U600, which pr3.3 V.
The SMA outputs are intended to drive 50
ȍ
loads to ground. Both outputs should be
terminated. (Without a terminator, the open emitter outputs of U202 will be biased “off”,
and there will be no clock at the SMA output.)
