Circuit Description
82
CG635 Synthesized Clock Generator
4.
Port-G is read to see if any keys have been pressed in the currently enabled
strobe column. Port-G is configured with active pull-downs to return the
KEY0-KEY5 to ground after the key is released.
5.
The sequence terminates with a return from interrupt instruction.
NPN emitter followers (Q500-Q506) are used to provide the required strobe line current.
PNP emitter followers (Q507-Q512) are used to provide the required lamp drive current.
High efficiency seven-segment displays are driven directly by the octal latches and do
not require emitter followers. Current in the seven segment displays is limited by N500
and N501 and current in the LED lamps is limited by N504-N506.
The front panel LED refresh could cause substantial interference at harmonics of 125 Hz
due to the 8 ms refresh interval. A large power supply capacitor, C514, is used as a
source for this large periodic current and the ground return path for the LED currents is
isolated from the other circuit grounds. The capacitor is charged from the +5_digital
supply via a L501.
A 10 ms one-shot, U505A, is used to disable the LED current drive if the
microcontroller stops generating –CS_STROBE signals. This prevents damaging the
LEDs (which are normally operated with a 1/8
th
duty factor) should the microcontroller
stop operating. The second half of U505 is used to generate a key-click sound when the
MSB of U508 is set high.
Rear-Panel RJ-45 Outputs
Main Board, Schematic sheet “CG_MB6D”
The clock and ±5 VDC are made available on the rear-panel RJ-45 connector (J604).
Both LDVS (pins 1 & 2) and RS-485 levels (pins 7 & 8) are available on the RJ-45
connector. The outputs are intended to drive unshielded twisted pair (UTP) CAT-6 cable
with 100
ȍ
terminations on the clock lines. The ±5 VDC supplies may be used to power
far-end line receivers. The current that may be drawn from these supplies is limited to
375 mA.
The RS-485 outputs are turned “off” above 105 MHz. The LVDS outputs operate up to
2.05 GHz. Internal PECL levels are translated to LVDS levels by the resistor networks
R622-R625. These resistor networks also reverse terminate the LVDS source with the
100
ȍ
characteristic impedance of the UTP cable.
The PECL clock is also used to drive the differential inputs of the RS-485 line driver
(U607), converting the clock to TTL levels. The open-emitter clock outputs from U605
will only be active when -EN_RS485 is low. When –EN_RS485 is high, the rear-panel
RS-485 outputs will be turned “off”.
An N-channel MOSFET (U612) pr5 VDC on the RJ-45 connector. The
MOSFET is turned “off” by U611A if the current seen in the shunt resistors (R617,
R618 & R641) exceeds 375 mA. A co-packaged Schottky diode in U612 prevents the +5
VDC from being pulled below ground.
