Circuit Description
72
CG635 Synthesized Clock Generator
An integrated 48-bit DDS (U200) is used to generate tunable reference frequencies
around 19.40 MHz or 19.44 MHz. The DDS provides complementary 12-bit current
source outputs at a sampling rate of 100 MHz. The stair-stepped current sources are ac
coupled by T200 and low-pass filtered by C213-C218 and L202-204. The sine-wave
output of the low-pass filter is converted to a reference clock by the AD8561
comparator, U203. A 19.40 MHz or a 19.44 MHz VCXO will be phase locked to this
signal with a narrow bandwidth. Doing so provides a spur-free reference of a VCXO
with the arbitrarily high frequency precision of a DDS.
The B-Port of the microcontroller (see sheet “CG_MB5D”) is used to read and write
data to the DDS registers via the bidirectional level shifter U503. Address and read/write
control bits for the DDS arrive via U502. The 20 MHz clock comes from the 20 MHz
timebase on Sheet 1, and is multiplied by 5× by a clock multiplier in U200.
The DDS output frequency is controlled by the 48-bit Frequency Tuning Word (FTW)
loaded in the DDS registers. The DDS has a Frequency Shift Key (FSK) input which
allows the DDS to shift between two different FTWs. This feature is used to extend the
frequency resolution of the 48-bit DDS by 16 bits to 64 bits in the following manner:
Two 48-bit (FTWs) are loaded into the registers of U200, FTW and FTW+1. By
applying a Pulse Width Modulated (PWM) signal (with 16 bits of duty cycle resolution)
to the FSK input, the DDS can operate with any FTW (with 16 bits of resolution)
between FTW and FTW+1. The frequency error associated with a ±1/2 LSB
quantization error in the 16-bit duty cycle of the FSK will cause a clock output to time
shift by 7 ps/year relative to an ideal source (which is considered to be negligible).
The two VCXOs, one at 19.40 MHz and the other at 19.44 MHz, operate continuously.
When the user enters a new operating frequency, the microcontroller determines which
VCXO will allow the RF synthesizer to generate the required RF frequency with the
lowest divisors, consistent with the ±100 ppm tuning restriction of the VCXOs. The
comparator for that VCXO is enabled and the selected VCXO will be phase-locked to
the tunable DDS source.
The two VCXOs are nearly identical. The 19.40 MHz VCXO will be described here:
The VCXO uses a Colpitts configuration consisting of Y200 with the series load
consisting of capacitors C256, C242 and C243 and the dual varactor D200. The crystal is
a fundamental mode, AT-cut, designed to operate with a parallel load 20 pF. The sine
wave output of the VCXO is converted to TTL levels by U205, which is enabled when
the logic signal ALT_REF is set high. (When ALT_REF is high, the comparator for the
19.44 MHz reference is latched.)
The symmetry of the selected VXCO reference is controlled by the integrator U204B
which compares the filtered output of the selected reference to Vcc/2. If the duty cycle
of the selected reference is low, the integrator output will ramp upward, increasing the
bias at the inverting input to the comparators (U205 and U210), and so increase the duty
cycle of the inverted outputs from the comparators.
The selected VCXO is phase locked to the DDS reference by a PLL which consists of
the phase/frequency detector (U207A, U207B and U208), a pre-filter (R217/C247 &
R218/C248), and an integrating loop filter (U204A and surrounding R’s and C’s). The
phase/frequency detector compares the phase of the DDS to the phase of the selected
VCXO. If the DDS leads in phase, then the output of the phase/frequency detector will
