Circuit Description
79
CG635 Synthesized Clock Generator
-RB_OPT:
This line is pulled low when the optional rubidium timebase is installed.
(The active pull-up for this port bit is enabled.)
-OCXO_OPT:
This line is pulled low when the optional Oven Controlled Crystal
Oscillator (OCXO) timebase is installed. (The active pull-up for this port bit is enabled.)
-PRBS_OPT:
This line is pulled low when the optional PRBS generator is installed.
(The active pull-up for this port bit is enabled.)
RF_LOCK:
This line goes high when the RF synthesizer has achieved phase-lock to the
19 MHz reference.
Microcontroller Outputs
PORT_A:
Data bus (8-bits) supplies data to nine octal latches. There is a corresponding
port strobe for each of the nine latches (ex: -CS_LAMP or –CS_ODD or –CS_EVEN).
Data is latched on the rising edge of the port strobe. Latches are operated from either
+5 V or +3.3 V as required by the target.
-CS_GPIB_CTL:
Port strobe for GPIB interface latch.
-CS_DDS_CTL:
Port strobe for DDS interface latch.
-CS_DDS:
Port strobe for DDS bi-directional (read or write) data transfer.
-CS_GPIB_CTL:
Port strobe for GPIB interface latch.
-CS_STROBE:
Port strobe for LED and KEY strobe line latch.
-CS_LAMP:
Port strobe for lamp LEDs latch.
-CS_ODD:
Port strobe odd-digit seven-segment LED display latch.
-CS_EVEN:
Port strobe even-digit seven-segment LED display latch.
-CS_SYN:
Chip select for dual-modulus synthesizer.
-CS_FLT:
Port strobe for RF PLL bandwidth control (& misc) latch.
-CS_DIV:
Port strobe for programmable ECL divider interface latch.
-CS_ECL:
Port strobe for ECL logic control interface latch.
-CS_DAC:
Port strobe for octal 12-bit DAC that supplies system analog voltages.
FSK_DDS:
Pulse width modulated signal whose duty cycle is controlled with 16 bits of
resolution to extend the resolution of the 48-bit DDS to 64 bits.
SDO:
Synchronous serial data output for data transfer to octal DAC and dual-modulus
synthesizer.
