Circuit Description
62
CG635 Synthesized Clock Generator
Typical results are –130 dBc/Hz at 1 kHz offset from a 10 MHz carrier, or –95 dBc/Hz
at 1 kHz offset from a 622.08 MHz carrier.
Circuit Block Diagram
A block diagram of the frequency synthesizer for the CG636 Synthesized Clock
Generator is shown on the first page of the schematic diagrams: CG_BLK_D. A
description of this diagram follows.
Timebase
The timebase for the synthesizer is a 20 MHz VCXO. The circuit uses a 20 MHz, 3
rd
overtone, AT-cut crystal. The VCXO will be phase locked to an external 10 MHz
reference if applied; otherwise, a digital-to-analog converter (DAC) provides an analog
voltage to calibrate the 20 MHz timebase. The 20 MHz timebase is used as a frequency
reference for the DDS which follows.
Reference Synthesizer
A 48-bit DDS uses the 20 MHz timebase as a reference to generate a frequency near
(i.e., within ±100 ppm) either 19,400,000 Hz or 19,440,000 Hz. The output of the DDS
synthesizer is used as a frequency reference for the RF synthesizer after being cleaned
up by a phase locked VCXO. The DDS has a clock multiplier which increases the
frequency sample clock by 5× to 100 MHz. The output frequency of the DDS is given
by the equation,
f
DDS
= sample clock × FTW / 2
64
= 100 MHz × FTW / 2
64
or
FTW = f
DDS
× 2
64
/ 100 MHz
The frequency resolution of the DDS is extended to 64 bits by toggling between a 48-bit
frequency tuning word (FTW) of k and k+1 with a duty factor that has 16 bits of
resolution.
The output of the DDS is low-pass filtered and converted to a square wave by a high
speed comparator. While the in-close phase noise of this reference is very good, there is
a thick forest of spurious components in the broadband spectrum below –80 dBc. These
spurs must be eliminated in order for the frequency reference to be useful for
synthesizing an RF output.
