Circuit Description
71
CG635 Synthesized Clock Generator
stable resets are avoided by stretching the reset pulse with D101, C134 and R138. For
propagation delay sums between 1.9 ns and 9 ns, and a period of 100 ns, the duty cycle
of the 3.3 V pulse is between 1.9 % and 9.0 % leading to a voltage of 63 mV to 297 mV
on the pre-filter outputs (10MHZ_LEAD and 10MHZ_LAG.) Hence the criteria for
phase lock of the 20 MHz timebase to an external or optional frequency reference is that
10MHZ_LEAD and 10MHZ_LAG be between 50 mV and 350 mV and within 20 mV of
each other.
If neither an external 10 MHz reference is applied nor an optional frequency reference is
installed, the microcontroller will set DAC/-PLL “high”, disabling the PLL and
pre-charging the PLL integrator to 3.66 × CAL_20MHZ control voltage. When
DAC/–PLL is “high”, the analog switches (U108) disconnect the phase/frequency
detector from the PLL integrator, ground the inverting input to the integrator, and apply
a feedback signal to the non-inverting input of the integrator. The feedback signal is the
difference between the output of the integrator divided by 11 and the filtered
CAL_20MHZ signal divided by 3. The integrator output, pin 1 of U109A, will slew until
the feedback signal is zero (i.e., to where the integrator output is equal to CAL_20MHZ
×11 / 3). Since CAL_20MHZ can be set between 0 and 4.095 VDC, the integrator output
can be set from 0 to 15 VDC.
Using this approach, prior to applying the external 10 MHz reference, the PLL integrator
will be pre-charged to the voltage for which the 20 MHz timebase was last calibrated.
Also, the microcontroller can calibrate the 20 MHz timebase finding the value of
CAL_20MHZ which provides the same voltage seen on 10MHZ_VC when the 20 MHz
timebase is locked to an accurate external reference.
DDS and the 19.40/19.44 MHz Reference
Main Board, Schematic sheet “CG_MB2D”
Clock outputs from the CG635 are generated by dividing down the output of an RF
synthesizer. The RF synthesizer operates between 950 MHz and 2050 MHz and is used
without division to provide clock outputs in that range.
The RF synthesizer used in this instrument (see sheet “CG_MB3D”) requires one of two
low-noise reference frequencies: 19.40 MHz or 19.44 MHz. Both of these references
need to be tuned over a range of ±100 ppm and need to be set with a resolution of 1:2
64
(about 1:2×10
19
).
The purpose of the circuitry on this page of schematics is to provide a low noise
19.40 MHz or 19.44 MHz reference for the RF synthesizer which is tunable over ±100
ppm with very high resolution.
Direct Digital Synthesis (DDS) allows the generation of the reference frequency with
arbitrary precision. However, DDS synthesizers have a rich spur spectrum that makes
them unsuitable for multiplication to high frequencies. This design uses a voltage
controlled crystal oscillator (VCXO) phase locked to a DDS reference by a narrow
bandwidth PLL to simultaneously achieve high frequency resolution and low spurious
components. The low-noise VCXO is then frequency multiplied by the dual-modulus RF
synthesizer to generate high frequency, low-noise clock outputs.
