Circuit Description
76
CG635 Synthesized Clock Generator
A differential clock fan-out driver (U405) is used to fan-out the selected clock to
multiple destinations: to (1) the front panel Q&Q
¯ driver, (2) the front panel CMOS
driver, (3) a low pass filter to allow the microcontroller’s ADC to measure the
top-octave symmetry, (4) rear panel LVDS and RS485 clock outputs, and (5) an optional
pseudo-random binary sequence generator. The clock driver can select between two
clock sources: when the bit –RUN/STOP is “low”, the clock driver selects the CLK0
input which is the output of the 1:4 ECL multiplexer; when –RUN/STOP is “high”, the
clock driver selects the CLK1 input which is the STOP_LVL bit from the
microcontroller. This allows the microcontroller to set the outputs high or low for
“half-stepping” and for calibration purposes. The clock driver outputs are enabled when
the –EN_OUT is low. The selected clock is enabled synchronously with its own falling
edge, thereby eliminating runt pulses. (The synchronous enable will require the
microcontroller to toggle the state of the STOP_LVL bit before it appears at the outputs,
and will cause a one-cycle delay in the enabling of free-running clocks.)
The differential PECL clocks for the front panel outputs connect to the driver daughter
board via J400. This connector also passes amplitude and offset control voltages and
power supplies to the front panel output driver board.
Microcontroller
Main Board, Schematic sheet “CG_MB5D”
The microcontroller (U500) is a MC68HC912D60A. The important features used in this
design include (1) 16-bit device with hardware math operations, (2) 60k bytes of flash
ROM for program instructions, (3) 2k bytes of RAM for volatile storage, (4) 1k byte of
EEPROM for calibration constants, (5) dual serial communication interfaces for two
RS-232 channels, (6) serial peripheral interface for communications with system
components, (6) 16-bit pulse width modulator for extending the resolution of the DDS
via its FSK input, (7) sixteen channels of 10-bit A/D conversion for testing and
calibration, (8) real-time interrupt generator, and (9) myriad I/O port bits for
system integration.
Analog Inputs to the Microcontroller
There are 16 analog inputs to the microcontroller. The full-scale range is 0-4.096 VDC
and the inputs are digitized with 10 bits of resolution (4.00 mV per bit). Details for each
of the sixteen inputs are given below.
EXT_DET
: Greater than 1.00 VDC indicates that an external 10 MHz reference has
been applied to the rear panel input and so the 20 MHz timebase should be phase-locked
to the external reference.
OPT_DET
: Greater than 1.00 VDC indicates that an optional 10 MHz reference is
installed and operating and so the 20 MHz timebase should be phase-locked to the
optional timebase if an external reference is not present.
10MHZ_LEAD:
Used to detect the phase-lock of the 20 MHz timebase to an external
or an optional timebase. 10MHZ_LEAD is a voltage proportional to the amount by
which the external reference or optional reference leads the 20 MHz timebase. The front-
panel UNLOCK LED will be lit if the instrument is trying to lock the 20 MHz timebase
