Operation 17
CG635 Synthesized Clock Generator
The Q / Q
¯ high and low voltages may be set to arbitrary values, or stepped up and down
by configurable step sizes by following the instructions described in the Front-Panel User
Interface section at the beginning of this chapter. However, the limits summarized in
Table 8 apply.
Table 8: Limits for Q / Q
¯ High and Low Voltages
Parameter Minimum
Maximum
Resolution
Q / Q
¯ HIGH (V
HIGH
)
–2.00 V
5.00 V
0.01 V
Q / Q
¯ LOW (V
LOW
)
–3.00 V
4.80 V
0.01 V
Q / Q
¯ Amplitude (V
HIGH
–V
LOW
)
0.20 V
1.00 V
0.01 V
Beware that a +5 V output will dissipate ½ watt into the target system’s 50
ȍ
termination.
If the user tries to enter a value that violates the V
HIGH
or V
LOW
limit, the CG635 will
briefly display “Volt Error” and leave the current value unchanged. However, if the user
tries to enter a value that is valid in terms of the limits on V
HIGH
and V
LOW
, but violates
the amplitude limit, the CG635 will change both the requested voltage and its
complement. The requested voltage will be set to the desired level, and the
complementary voltage will be adjusted to satisfy the amplitude limits. The CG635 will
briefly display “lo is N.NN” or “hi is N.NN” to indicate the new complementary voltage
level. If V
HIGH
– V
LOW
would be > 1.00 V, V
LOW
will be set 1.00 V below V
HIGH
or V
HIGH
will be set 1.00 V above V
LOW
. If V
HIGH
– V
LOW
would be < 0.20 V, V
LOW
will be set
0.20 V below V
HIGH
or V
HIGH
will be set 0.20 V above V
LOW
.
For example, if the outputs are currently at LVDS levels, setting V
HIGH
to 5.5 V will
cause the CG635 to briefly display “Volt Error” and leave the outputs unchanged,
because 5.5 V exceeds the upper limit for V
HIGH
. On the other hand, setting V
HIGH
to
5.0 V will cause the CG635 to briefly display “Lo is 4.00” and to set V
HIGH
and V
LOW
to
5.00 V and 4.00 V, respectively. V
LOW
is adjusted in addition to V
HIGH
in order to satisfy
the amplitude limits.
CMOS Output
The CMOS output provides CMOS compatible voltages at a 50 % duty cycle. The
transition times of this output are less than 1.0 ns (10% to 90%). It drives the output at the
selected frequency, amplitude and offset for frequencies ranging from DC to 250 MHz.
At frequencies above 250 MHz, the CMOS driver will be turned off and forced to a low
logic state.
Despite its relatively high speed, the CMOS output should not be terminated with a 50
ȍ
load. Terminating the output will not harm the instrument but it will divide the output
voltage levels in half. The CMOS output has a 50
ȍ
source impedance and so will
reverse terminate pulses which are reflected back from the user’s (unterminated) target
system. For CMOS levels below 2.50 V, the user may wish to terminate the CMOS
output with a 50
ȍ
load and set the output levels to twice that required by the user’s
target system. Doing so will somewhat improve the rise time and reduce reflected clocks
edges on the output.
