Circuit Description
77
CG635 Synthesized Clock Generator
to either an external or an optional timebase and the 10MHZ_LEAD and 10MHZ_LAG
are not between 50 mV and 350 mV or not within 20 mV of each other.
10MHZ_LAG:
Used to detect the phase-lock of the 20 MHz timebase to an external or
an optional timebase. 10MHZ_LAG is a voltage proportional to the amount by which
the external reference or optional reference lags the 20 MHz timebase. The front-panel
UNLOCK LED will be lit if the instrument is trying to lock the 20 MHz timebase to
either an external or an optional timebase and the 10MHZ_LEAD and 10MHZ_LAG are
not between 50 mV and 350 mV or not within 20 mV of each other.
10MHZ_VC:
Scaled (by 0.285×) and filtered (with about 500 Hz bandwidth) version of
the varactor voltage that controls the frequency of the 20 MHz VCXO timebase. The
front-panel UNLOCK LED will be lit if the instrument is trying to lock the 20 MHz
timebase to either an external or an optional timebase and the 10MHZ_VC is less than
0.25 V or greater than 3.75 V. (These thresholds may change.)
19MHZ_LEAD:
Used to detect the phase-lock of the 19.4 MHz timebase to the DDS.
19MHZ_LEAD is a voltage proportional to the amount by which DDS leads the
19.4 MHz VCXO. The front panel UNLOCK LED will be lit if 19MHZ_LEAD and
19MHZ_LAG are not between 100 mV and 600 mV or not within 20 mV of each other.
19MHZ_LAG:
Used to detect the phase-lock of the 19.4 MHz timebase to the DDS.
19MHZ_LAG is a voltage proportional to the amount by which DDS lags the 19.4 MHz
VCXO. The front panel UNLOCK LED will be lit if 19MHZ_LEAD and 19MHZ_LAG
are not between 100 mV and 600 mV or not within 20 mV of each other.
19MHZ_VC:
Scaled (by 0.285×) and filtered (with about 500 Hz bandwidth) version of
the varactor voltage that controls the frequency of the 19.4 MHz VCXO timebase. The
front panel UNLOCK LED will be lit if 19MHZ_VC is less than 0.25 V or greater than
3.75 V. (These thresholds may change.)
10mV/C:
Analog voltage proportion to the PCB temperature in °C. Scale factor is
10 mV/°C with zero intercept. (Example: 300 mV at 30°C)
RF_VC:
Scaled (by 0.210×) and filtered (with about 50 Hz bandwidth) version of the
varactor voltage that controls the frequency of the RF VCO. The front panel UNLOCK
LED will be lit if RF_VC is less than 0.20 V or greater than 3.00 V. (These thresholds
may change.)
+CLK_TST:
Analog voltage equal to the average voltage (with 1 ms time constant) of
the non-inverted PECL clock source. The signal is useful for measuring the duty cycle of
the top octave clock signal when compared to –CLK_TST. The analog DAC voltage
CAL_SYM will be adjusted to eqCLK_TST and –CLK_TST to assure 50/50
duty cycle in the top octave.
-CLK_TST:
Analog voltage equal to the average voltage (with 1 ms time constant) of
the inverted PECL clock source. The signal is useful for measuring the duty cycle of the
top octave clock signal when compared to +CLK_TST. The analog DAC voltage
CAL_SYM will be adjusted to eqCLK_TST and –CLK_TST to assure 50/50
duty cycle in the top octave.
