User Manual 3153
Specifications A-1
Appendix A
SPECIFICATIONS
VXlbus General Information
Module Form
Single slot VXlbus C-size module
Connectors
P1, P2
Protocol
A24/A32/D16 Slave, Message-Based
VXlbus Revision
2.0
SCPI Revision
1993.0
Logical Address Settings
1 - 255, configured via DIP switches
Interrupt Level Settings
1 - 7, configured dynamically (no DIP switch)
Shared Memory (Write only)
A24, A32, D16
Module General Information
Configuration
Three independent waveform generators
Master/Slave Configuration
Master channel (100MS/s channel) provides sample clock for
slave channels. Each slave channel can divide the sample
clock down by an integer from 1 to 64k. Only the 100MS/s
Channel is configurable as master, either or both 50MS/s
channels are configurable as slaves. Phase offsets, in
reference to channel 1, can be applied to channels 2 and 3
Independent Configuration
Each channel uses its own sample clock and trigger.
Synchronization Modes
Description
Each waveform generator can operate in one of three main
modes. Each mode can be synchronized and or triggered as
indicated.
Synchronization
Only the 100 MSa/s Channel is configurable as master, either
or both 50 MSa/s channels are configurable as slaves. The
master clock source may be internal or external. The sample
clock may be divided from 1-64K on channels 2 and 3. Master
Slave configuration is for User and Sequence Modes.
Output Waveforms
Fixed (standard)
The waveform generator outputs one of nine standard, pre-
defined waveform.
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