User Manual 3153
Maintenance and Performance Checks 5-13
Sample Clock Source and
Dividers
1. Program all three channels as follows:
Operating mode: User (arbitrary).
FUNC:MODE USER
Sample clock frequency: 100 MSa/s for channel 1; 50 MSa/s for
channels 2/3.
FREQ:RAST 100E6;:INST:SEL 2;:FREQ:RAST
50E6;:INST:SEL 3;:FREQ:RAST 50E6
Waveform: Download 100-point squarewave
WaveCAD, axis 100 points, wave square, download
Clock Dividers 2/3: 1
INST:SEL 2;:FREQ:RAST:DIV 1;:INST:SEL 3;:FREQ:RAST:DIV 1
2. Test the sample clock source and dividers using Table 5-8
Table 5-8, Sample Clock Source Tests.
Channel 2,3
Counter Reading
SCLK Source
Divider
CH 1
CH 2
CH 3
Pass
Fail
Ch 1,2,3 – Int
1
500kHz
500kHz
500kHz
INST:SEL 2|3;:FREQ:RAST:SOUR EXT
1
500kHz
500kHz
500kHz
INST:SEL 1;:FREQ:RAST:SOUR EXT
INST:SEL 2|3;:FREQ:RAST:SOUR INT
1
500kHz
500kHz
500kHz
INST:SEL 2|3;:FREQ:RAST:SOUR EXT
1
500kHz
500kHz
500kHz
INST:SEL 1|2|3;:FREQ:RAST:SOUR INT
INST:SEL 2|3;:FREQ:RAST:DIV 100
500kHz
5kHz
5kHz
Ch 1,2,3 – Int
INST:SEL 2|3;:FREQ:RAST:DIV 1000
500kHz
500Hz
500Hz
Ch 1,2,3 – Int
INST:SEL 2|3;:FREQ:RAST:DIV 10000
500kHz
50Hz
50Hz
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