86
Computing the Cycle Time
Section 2-7
Calculation Example
Conditions:
Input ON delay
1 ms (normal input with input
constant set to 0 ms)
Output ON delay
0.1 ms (transistor output)
Cycle time
20 ms
Minimum I/O response time = 1 ms + 20 ms + 0.1 ms = 21.1 ms
Maximum I/O response time = 1 ms + (20 ms
×
2) + 0.1 ms = 41.1 ms
Input Response
Times
Input response times can be set in the PLC Setup. Increasing the response
time reduces the effects of chattering and noise. Decreasing the response
time allows reception of shorter input pulses, (but the pulse width must be
longer than the cycle time).
PLC Setup
2-7-8
Interrupt Response Times
Input Interrupt Tasks
The interrupt response time for I/O interrupt tasks is the time taken from when
a built-in input has turned ON (or OFF) until the I/O interrupt task has actually
been executed. The length of the interrupt response time for I/O interrupt
tasks depends on the following conditions.
Note
(1) The wait time occurs when there is competition with other interrupts. As
a guideline, the wait time will be 6 to 169
µ
s.
(2) I/O interrupt tasks can be executed during execution of the user program
(even while an instruction is being executed by stopping the execution of
an instruction), I/O refresh, peripheral servicing, or overseeing. The inter-
rupt response time is not affected by which of the above processing op-
erations during which the interrupt inputs turns ON. I/O interrupts,
however, are not executed during execution of other interrupt tasks even
if the I/O interrupt conditions are satisfied. Instead, the I/O interrupts are
Input
Input response time
Input
I/O refresh
CPU Unit
CPU Unit
Input response time
The pulse width is
less than the input
response time, so
it is not detected.
I/O refresh
Name
Description
Settings
Default
Input constants
Input response times 00 hex: 8 ms
10 hex: 0 ms
11 hex: 0.5 ms
12 hex: 1 ms
13 hex: 2 ms
14 hex: 4 ms
15 hex: 8 ms
16 hex: 16 ms
17 hex: 32 ms
00 hex (8 ms)
Item
Interrupt response time
Counter interrupts
Hardware response
Rise time: 50
µ
s
---
Fall time: 50
µ
s
---
Software interrupt
response
Minimum: 134
µ
s
Minimum: 236
µ
s
Maximum: 234
µ
s + Wait
time (See note 1.)
Maximum: 336
µ
s + Wait time
(See note1.)
Summary of Contents for CP1L-L14D Series
Page 2: ...CP1L L14D CP1L L20D CP1L M30D CP1L M40D CP1L CPU Unit Operation Manual Revised June 2007...
Page 3: ...iv...
Page 9: ...x...
Page 13: ...xiv TABLE OF CONTENTS...
Page 21: ...xxii...
Page 33: ...xxxiv Conformance to EC Directives 6...
Page 65: ...32 Function Blocks Section 1 5...
Page 153: ...120 CP CPM1A series Expansion I O Unit Wiring Section 3 6...
Page 523: ...490 Troubleshooting Unit Errors Section 9 4...
Page 531: ...498 Replacing User serviceable Parts Section 10 2...
Page 563: ...530 Auxiliary Area Allocations by Function Appendix C...
Page 611: ...578 Auxiliary Area Allocations by Address Appendix D...
Page 638: ...605 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 639: ...606 Connections to Serial Communications Option Boards Appendix F...
Page 669: ...636 Index...
Page 671: ...638 Revision History...