159
High-speed Counters
Section 5-1
5-1-2
High-speed Counter Specifications
Specifications
Item
Specification
Number of high-speed counters
2 (High-speed counters 0 and 1)
4 (High-speed
counters 0 to 3)
Pulse input modes (Selected in the PLC
Setup)
Differential phase
inputs
Up/down inputs
Pulse + direction
inputs
Increment inputs
Input terminal allocation
Phase-A input
Increment pulse
input
Pulse input
Increment pulse
input
Phase-B input
Decrement pulse
input
Direction input
---
Phase-Z input
Reset input
Reset input
Reset input
Input method
Differential phase,
4x
(Fixed)
Two single-phase
inputs
Single-phase
pulse + direction
inputs
Single-phase
input
Response frequency
50 kHz
100 kHz
100 kHz
100 kHz
Counting mode
Linear mode or circular (ring) mode (Select in the PLC Setup.)
Count values
Linear mode: 8000 0000 to 7FFF FFFF hex
Ring mode: 0000 0000 to Ring SV
(The Ring SV (Circular Max. Count) is set in the PLC Setup and the setting
range is 00000001 to FFFFFFFF hex.)
High-speed counter PV storage locations
High-speed counter 0: A271 (leftmost 4 digits) and A270 (rightmost 4 digits)
High-speed counter 1: A273 (leftmost 4 digits) and A272 (rightmost 4 digits)
High-speed counter 2: A317 (leftmost 4 digits) and A316 (rightmost 4 digits)
High-speed counter 3: A319 (leftmost 4 digits) and A318 (rightmost 4 digits)
Target value comparison interrupts or range comparison interrupts can be
executed based on these PVs.
Note
The PVs are refreshed in the overseeing processes at the start of each
cycle. Use PRV(881) to read the most recent PVs.
Data format: 8 digit hexadecimal
Range in linear mode: 8000 0000 to 7FFF FFFF hex
Range in ring mode: 0000 0000 to Ring SV (Circular Max. Count)
Control
method
Target value comparison
Up to 48 target values and corresponding interrupt task numbers can be reg-
istered.
Range comparison
Up to 8 ranges can be registered, with a separate upper limit, lower limit, and
interrupt task number for each range.
Counter reset method
Select one of the following methods in the PLC Setup.
•Phase-Z + Software reset
The counter is reset when the phase-Z input goes ON while the Reset Bit is
ON.
•Software reset
The counter is reset when the Reset Bit goes ON.
(Set the counter reset method in the PLC Setup.)
Note
Operation can be set to stop or continue the comparison operation
when the high-speed counter is reset.
Summary of Contents for CP1L-L14D Series
Page 2: ...CP1L L14D CP1L L20D CP1L M30D CP1L M40D CP1L CPU Unit Operation Manual Revised June 2007...
Page 3: ...iv...
Page 9: ...x...
Page 13: ...xiv TABLE OF CONTENTS...
Page 21: ...xxii...
Page 33: ...xxxiv Conformance to EC Directives 6...
Page 65: ...32 Function Blocks Section 1 5...
Page 153: ...120 CP CPM1A series Expansion I O Unit Wiring Section 3 6...
Page 523: ...490 Troubleshooting Unit Errors Section 9 4...
Page 531: ...498 Replacing User serviceable Parts Section 10 2...
Page 563: ...530 Auxiliary Area Allocations by Function Appendix C...
Page 611: ...578 Auxiliary Area Allocations by Address Appendix D...
Page 638: ...605 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 639: ...606 Connections to Serial Communications Option Boards Appendix F...
Page 669: ...636 Index...
Page 671: ...638 Revision History...