NXP Semiconductors MCF5253, Reference Manual

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Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
20-30 Freescale Semiconductor
Figure 20-28. Debug Programming Mode
20.5.1 Address Breakpoint Registers
The address breakpoint registers (ABLR and ABHR) define a region in the operand address space of the
processor that can be used as part of the trigger. The full 32-bits of the ABLR and ABHR values are
compared with the address for all transfers on the processor’s high-speed local bus. The trigger definition
register (TDR) determines if the trigger is the inclusive range bound by ABLR and ABHR, all addresses
outside this range, or the address in ABLR only. The ABHR is accessible in supervisor mode as debug
control register $C using the WDEBUG instruction and through the BDM port using the RDMREG and
WDMREG commands. The ABLR is accessible in supervisor mode as debug control register $D using the
WDEBUG instruction and through the BDM port using the WDMREG commands. The ABHR is
overwritten by the BDM hardware when accessing memory as described in
Section 20.4.1.2, “Debug
Module Hardware.”
ADDRESS[31:0]–Low Address
This field contains the 32-bit address which marks the lower bound of the address breakpoint range.
Additionally, if a breakpoint on a specific address is required, the value is programmed into the ABLR.
Access: User write only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
ADDRESS[31:0]
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ADDRESS[31:0]
Reset – – – – – – – – – – – – – – – –
Figure 20-29. Address Breakpoint Low Register (ABLR)
Address
Breakpoint Registers
PC Breakpoint
Registers
Data Breakpoint
Registers
ABLR
ABHR
PBR
PBMR
DBMR
DBR
TDR
15
0
31
Trigger Definition
Register
Address Attribute
Trigger Register
AATR
7
0
15
CSR
Configuration/Status Register
BDM ADDRESS Attribute
Register
BAAR