NXP Semiconductors MCF5253, Reference Manual

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Static RAM (SRAM)
MCF5253 Reference Manual, Rev. 1
6-2 Freescale Semiconductor
• The RAMBAR register holds the base address of the SRAM. The MOVEC instruction provides
write-only access to this register.
• The RAMBAR registers can be read or written from the Debug module in a similar manner.
• All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR, and return zeroes when read from the debug module.
• The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are
unaffected.
The RAMBAR register contains several control fields. These fields are detailed in the following tables.
NOTE
All unused bits in the RAMBAR register must be initialized to zero
Address
CPU + $C04
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
W
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BA15 BA14 WP C/I SC SD UC UD V
W
Reset – – – – – – – – – – – – – – – 0
Figure 6-1. SRAM Base Address Register (RAMBAR0)
Address
CPU + $C05
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
W
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BA15 BA14 PRI1 PRI2 SPV WP C/I SC SD UC UD V
W
Reset – – – – – – – – – – – – – – – 0
Figure 6-2. SRAM1 Base Address Register (RAMBAR1)