System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
9-3
9.3
SIM Module Programming Registers
This section provides the Module Base Address, DeviceID, and Interrupt Controller registers and their
descriptions.
9.3.1
Module Base Address Registers
The base address of all internal peripherals is determined by the MBAR and MBAR2 registers.
The MBAR and MBAR2 are 32-bit write-only supervisor control registers that physically reside in the
SIM. They are accessed in the CPU address spaces $C0F and $C0E using the MOVEC instruction. Refer
to the
ColdFire Family Programmer’s Reference Manual
for use of MOVEC instruction. The MBAR and
MBAR2 can be read when in debug mode using background debug commands.
At system reset, the MBAR valid bits (MBAR[0], MBAR2[0]) are cleared to prevent incorrect reference
to resources before the MBAR or MBAR2 are written. The remainder of the MBAR and MBAR2 bits are
MBAR + $054
Primary Interrupt Control Reg
ICR8
ICR9
ICR10
ICR11
MBAR2 + $000
GPIO 0
–
31 input reg
GPIO-READ (READ ONLY)
MBAR2 + $004
GPIO 0
–
31 output reg
GPIO-OUT
MBAR2 + $008
GPIO 0
–
31 output enable reg
GPIO-ENABLE
MBAR2 + $00C
GPIO 0
–
31 function select
GPIO-FUNCTION
MBAR + $0AC
DeviceID Reg
–
MBAR2 + $0B0
GPIO 32
–
63 input reg
GPIO1-READ (READ ONLY)
MBAR2 + $0B4
GPIO 32
–
63 output reg
GPIO1-OUT
MBAR2 + $0B8
GPIO 32
–
63 output enable reg
GPIO1-ENABLE
MBAR2 + $0BC
GPIO 32
–
63 function select
GPIO1-FUNCTION
MBAR2 + $140
Secondary interrupts 0
–
7 priority
INTPRI1
MBAR2 + $144
Secondary interrupts 8
–
15 priority
INTPRI2
MBAR2 + $148
Secondary interrupts 16
–
23 priority
INTPRI3
MBAR2 + $14C
Secondary interrupts 24
–
31 priority
INTPRI4
MBAR2 + $150
Secondary interrupts 32
–
39 priority
INTPRI5
MBAR2 + $154
Secondary interrupts 40
–
47 priority
INTPRI6
MBAR2 + $158
Secondary interrupts 48
–
55 priority
INTPRI7
MBAR2 + $15C
Secondary interrupts 56
–
63 priority
INTPRI8
MBAR2 + $164
Spurious secondary interrupt vector
SPURVEC
MBAR2 + $168
Secondary interrupt base vector register
INTBASE
MBAR2 + $198
Software interrupts and interrupt monitor
EXTRAINT
Table 9-2. SIM Memory Map (continued)
Address
Description
0
1
2
3
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
