NXP Semiconductors MCF5253, Reference Manual

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Static RAM (SRAM)
MCF5253 Reference Manual, Rev. 1
6-4 Freescale Semiconductor
6.3.2 SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the RAMBAR
is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the
following steps should be performed:
1. Load the RAMBAR mapping the SRAM module to the desired location within the address space
and set the Valid bit.
2. Read the source data and write it to the SRAM. There are various instructions to support this
function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM
instruction is optimized to generate line-sized burst fetches on modulo-64 addresses, so this opcode
generally provides maximum performance.
3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into
the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address
space mask fields.
The ColdFire processor or an external emulator using the debug module can perform these initialization
functions.
6.3.3 SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address of the
SRAM at $20000000 and then initializes the RAM to zeros.
RAMBASE EQU $20000000; set this variable to $20000000
RAMVALID EQU $00000001;
move.l #RAMVALID,D0;load R valid bit into D0.
movec.l D0, RAMBAR;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero
lea.l RAMBASE,A0;load pointer to SRAM
move.l #4096,D0;load loop counter into D0
SRAM_INIT_LOOP:
clr.l (A0)+); clear 4 bytes of SRAM
subq.l #1,D0;decrement loop counter
bne.b SRAM_INIT_LOOP;if done, then exit; else continue looping
6.3.4 Power Management
As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch and
operand read accesses may be sent to the SRAM and unified cache simultaneously. If the access is mapped
to the SRAM module, it sources the read data, and the unified cache access is discarded. If the SRAM is
used only for data operands, asserting the ASn bits associated with instruction fetches can decrease power
dissipation. Additionally, if the SRAM contains only instructions, masking data accesses can reduce power
dissipation.
Table 6-2 shows some examples of typical RAMBAR settings.